"... In PAGE 7: ... The serial PROM which stores the programmed mode bits will have to drive the ModeIn pin prior to the rising edge of the ModeClock, as per required data setup (TMDS) and hold time (TMDH). There are a total of 256 mode bits (see Table2 -1). The values of all the reserved bits must be set to a logic low or else the operation of the VR4000 is undefined.... In PAGE 8: ... The ModeClock signal will continue to toggle after reading in the mode bits until ColdReset* is reasserted. The bit# 63 of the mode bits allows the user to select the VR4000 to run with the PLL enabled or disabled (see Table2 -1). The normal operation of the processor with the PLL disabled is not supported and this mode is used for debugging of the silicon only.... In PAGE 8: ... The MasterOut and SyncOut will be stable when the ColdReset* is de-asserted; but the SClock, RClock amp; TClock will stablize 64 MasterClock cycles after the ColdReset* is de-asserted1. Although, it could be assumed that, regardless of which SysCkRatio (mode bits 15:17 in Table2 -1) the system interface is operating, the rising edge of PClock, SClock, RClock amp; TClock will be synchronized to the first rising edge of the MasterClock after the de- assertion of the ColdReset* signal. After the de-assertion of the ColdReset* signal, the Reset* signal needs to be asserted for at least 64 MasterClock cycles before the VR4000 is completely reset.... In PAGE 10: ... Table2 -1: Boot-Mode Settings Serial Bit Value Mode Setting 0 BlkOrder: Secondary Cache Mode block read response ordering 0 Sequential ordering 1 Subblock ordering 1 EIBParMode: Specifies nature of System interface check bus 0 Single error correcting, double error detecting (SECDED) error checking and correcting mode 1 Byte parity 2 EndBIt: Specifies byte ordering 0 Little-endian ordering 1 Big-endian ordering 3 DShMdDis: Dirty shared mode; enables the transition to dirty shared state on a successful processor update 0 Dirty shared mode enabled 1 Dirty shared mode disabled 4 NoSCMode: Specifies presence of secondary cache 0 Secondary cache present 1 No secondary cache present 5:6 SysPort: System Interface port width, bit 6 most significant 0 64 bits 1-3 Reserved 7 SC64BitMd: Secondary cache interface port width 0 128 bits 1 Reserved 8 EISpltMd: Specifies secondary cache organization 0 Secondary cache unified 1... In PAGE 11: ...7 Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 9:10 SCBlkSz: Secondary cache line length, bit 10 most significant 0 4 words 1 8 words 2 16 words 3 32 words 11:14 XmitDatPat: System interface data rate, bit 14 most significant 0 D 1 DDx 2 DDxx 3 DxDx 4 DDxxx 5 DDxxxx 6 DxxDxx 7 DDxxxxxx 8 DxxxDxxx 9-15 Reserved 15:17 SysCkRatio: PClock to SClock divisor, frequency relationship between SClock, RClock, and TClock and PClock, bit 17 most significant 0 Divide by 2 1 Divide by 3 2 Divide by 4 3 Divide by 6 (R4400 processor only) 4 Divide by 8 (R4400 processor only) 5-7 Reserved 18 SIMasterMd: Master/Checker Mode (see mode bit 42); used in R4400 only.... In PAGE 12: ...VR4000/VR4400 Reset and Initialization Sequence Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 25:26 TWr2Dly: Secondary cache write assertion delay 2, TWr2Dly in PCycles, bit 26 most significant 0 1-3 Undefined Number of PClock cycles: Min 1, Max 3 27:28 TWr1Dly: Secondary cache write assertion delay 1, TWr1Dly in PCycles, bit 28 most significant 0 1-3 Undefined Number of PClock cycles; Min 1, Max 3 29 TWrRc: Secondary cache write recovery time, TWrRc in PCycles, either 0 or 1 cycle 0 1 0 cycle 1 cycle 30:32 TDis: Secondary cache disable time, TDis in PCycles, bit 32 most significant 0-1 2-7 Undefined Number of PClock cycles: Min 2, Max 7 33:36 TRd2Cyc: Secondary cache read cycle time 2, TRdCyc2 in PCycles, bit 36 most significant 0-2 3-15 Undefined Number of PClock cycles: Min 3, Max 15 37:40 TRd1Cyc: Secondary cache read cycle time 1, TRdCyc1 in PCycles, bit 40 most significant 0-3 4-15 Undefined Number of PClock cycles: Min 4, Max 15 41 0 Reserved 42 SCMasterMd: selects the type of Master/Checker mode (also see description of mode bit 18).... In PAGE 13: ...9 Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 46 Pkg179: R4000 Processor Package type 0 1 Large (447 pin) Small (179 pin) 47:49 CycDivisor: This mode determines the clock divisor for the reduced power mode.... In PAGE 14: ...VR4000/VR4400 Reset and Initialization Sequence Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 63 DsblPLL: Disables the phase-locked loops (PLLs) that match MasterClock and produce RClock, TClock, SClock, and the internal clocks.... In PAGE 25: ... The initialization of the mode bits, during the boot time, provides a great amount of flexibility to users in terms of processor configuration and operating parameters. These mode bits were described in chapter 2 ( Table2 -1). The initialization of caches and TLBs is done from the exception handler and the procedure was described via a pseudo code.... ..."

"... In PAGE 7: ... The serial PROM which stores the programmed mode bits will have to drive the ModeIn pin prior to the rising edge of the ModeClock, as per required data setup (TMDS) and hold time (TMDH). There are a total of 256 mode bits (see Table2 -1). The values of all the reserved bits must be set to a logic low or else the operation of the VR4000 is undefined.... In PAGE 8: ... The ModeClock signal will continue to toggle after reading in the mode bits until ColdReset* is reasserted. The bit# 63 of the mode bits allows the user to select the VR4000 to run with the PLL enabled or disabled (see Table2 -1). The normal operation of the processor with the PLL disabled is not supported and this mode is used for debugging of the silicon only.... In PAGE 8: ... The MasterOut and SyncOut will be stable when the ColdReset* is de-asserted; but the SClock, RClock amp; TClock will stablize 64 MasterClock cycles after the ColdReset* is de-asserted1. Although, it could be assumed that, regardless of which SysCkRatio (mode bits 15:17 in Table2 -1) the system interface is operating, the rising edge of PClock, SClock, RClock amp; TClock will be synchronized to the first rising edge of the MasterClock after the de- assertion of the ColdReset* signal. After the de-assertion of the ColdReset* signal, the Reset* signal needs to be asserted for at least 64 MasterClock cycles before the VR4000 is completely reset.... In PAGE 10: ...VR4000/VR4400 Reset and Initialization Sequence 2.2 Boot-Mode Settings Table2 -1 lists the processor boot-mode settings and the timing is shown in figure 2.1.... In PAGE 11: ...7 Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 9:10 SCBlkSz: Secondary cache line length, bit 10 most significant 0 4 words 1 8 words 2 16 words 3 32 words 11:14 XmitDatPat: System interface data rate, bit 14 most significant 0 D 1 DDx 2 DDxx 3 DxDx 4 DDxxx 5 DDxxxx 6 DxxDxx 7 DDxxxxxx 8 DxxxDxxx 9-15 Reserved 15:17 SysCkRatio: PClock to SClock divisor, frequency relationship between SClock, RClock, and TClock and PClock, bit 17 most significant 0 Divide by 2 1 Divide by 3 2 Divide by 4 3 Divide by 6 (R4400 processor only) 4 Divide by 8 (R4400 processor only) 5-7 Reserved 18 SIMasterMd: Master/Checker Mode (see mode bit 42); used in R4400 only.... In PAGE 12: ...VR4000/VR4400 Reset and Initialization Sequence Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 25:26 TWr2Dly: Secondary cache write assertion delay 2, TWr2Dly in PCycles, bit 26 most significant 0 1-3 Undefined Number of PClock cycles: Min 1, Max 3 27:28 TWr1Dly: Secondary cache write assertion delay 1, TWr1Dly in PCycles, bit 28 most significant 0 1-3 Undefined Number of PClock cycles; Min 1, Max 3 29 TWrRc: Secondary cache write recovery time, TWrRc in PCycles, either 0 or 1 cycle 0 1 0 cycle 1 cycle 30:32 TDis: Secondary cache disable time, TDis in PCycles, bit 32 most significant 0-1 2-7 Undefined Number of PClock cycles: Min 2, Max 7 33:36 TRd2Cyc: Secondary cache read cycle time 2, TRdCyc2 in PCycles, bit 36 most significant 0-2 3-15 Undefined Number of PClock cycles: Min 3, Max 15 37:40 TRd1Cyc: Secondary cache read cycle time 1, TRdCyc1 in PCycles, bit 40 most significant 0-3 4-15 Undefined Number of PClock cycles: Min 4, Max 15 41 0 Reserved 42 SCMasterMd: selects the type of Master/Checker mode (also see description of mode bit 18).... In PAGE 13: ...9 Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 46 Pkg179: R4000 Processor Package type 0 1 Large (447 pin) Small (179 pin) 47:49 CycDivisor: This mode determines the clock divisor for the reduced power mode.... In PAGE 14: ...VR4000/VR4400 Reset and Initialization Sequence Table2 -1 (cont.) Boot-Mode Settings Serial Bit Value Mode Setting 63 DsblPLL: Disables the phase-locked loops (PLLs) that match MasterClock and produce RClock, TClock, SClock, and the internal clocks.... In PAGE 25: ... The initialization of the mode bits, during the boot time, provides a great amount of flexibility to users in terms of processor configuration and operating parameters. These mode bits were described in chapter 2 ( Table2 -1). The initialization of caches and TLBs is done from the exception handler and the procedure was described via a pseudo code.... ..."

"... In PAGE 11: ... The i-protocol is part of the protocol stack of the GNU UUCP package available from the Free Software Foundation, and consists of about 300 lines of C code. Table1 contains the execution-time and memory-usage requirements for XMC,... In PAGE 12: ...8GB of available main memory. As can be observed from Table1 , XMC performs exceptionally well on this demanding benchmark. This can be attributed to the power of the underlying Prolog data structuring facility (the i-protocol makes use of non-trivial data structures such as arrays and records), and the fact that data structures in XSB are evaluated lazily.... ..."

"... In PAGE 11: ... The i-protocol is part of the protocol stack of the GNU UUCP package available from the Free Software Foundation, and consists of about 300 lines of C code. Table1 contains the execution-time and memory-usage requirements for XMC,... In PAGE 12: ...8GB of available main memory. As can be observed from Table1 , XMC performs exceptionally well on this demanding benchmark. This can be attributed to the power of the underlying Prolog data structuring facility (the i-protocol makes use of non-trivial data structures such as arrays and records), and the fact that data structures in XSB are evaluated lazily.... ..."

"... In PAGE 11: ... The i-protocol is part of the protocol stack of the GNU UUCP package available from the Free Software Foundation, and consists of about 300 lines of C code. Table1 contains the execution-time and memory-usage requirements for XMC,... In PAGE 12: ...8GB of available main memory. As can be observed from Table1 , XMC performs exceptionally well on this demanding benchmark. This can be attributed to the power of the underlying Prolog data structuring facility (the i-protocol makes use of non-trivial data structures such as arrays and records), and the fact that data structures in XSB are evaluated lazily.... ..."

"... In PAGE 12: ... The i-protocol is part of the protocol stack of the GNU UUCP package available from the Free Software Foundation, and consists of about 300 lines of C code. Table1 contains the execution-time and memory-usage requirements for XMC, SPIN, COSPAN [HHK96], and SMV [CMCHG96] applied to the i-protocol to detect a non-trivial livelock error that can occur under certain message-loss conditions. This livelock error was rst detected using the Concurrency Factory.... In PAGE 12: ...8GB of available main memory. As can be observed from Table1 , XMC performs exceptionally well on this demanding benchmark. This can be attributed to the power of the underlying Prolog data structuring facility (the i-protocol makes use of non-trivial data structures such as arrays and records), and the fact that data structures in XSB... ..."

"... In PAGE 14: ... The time base for the PLL_LOCKCNT register is the period of CLKIN. BOOTING MODES The ADSP-BF561 has three mechanisms (listed in Table7 ) for automatically loading internal L1 instruction memory, L2, or external memory after a reset. A fourth mode is provided to exe- cute from external memory, bypassing the boot sequence.... ..."

"... In PAGE 14: ... This programmable core clock capability is useful for fast core frequency modifications. BOOTING MODES The ADSP-BF531/ADSP-BF532 processor has two mechanisms (listed in Table8 ) for automatically loading internal L1 instruc- tion memory after a reset. A third mode is provided to execute from external memory, bypassing the boot sequence.... ..."

"... In PAGE 79: ... The spike shape of the R2 model is obviously quite di erent from the FULL and R1 models. Even with this significant change in the structure of the model, however, the period, duty cycle, and slow-wave characteristics of the FULL-R2 half-center oscillator are very similar to FULL-FULL half-center oscillator ( Table1 ). Only the spike frequency characteristics of the R2 model are noticeably di erent from the FULL-FULL half-center (Table 2).... ..."

"... In PAGE 9: ... In our approach, we decided to adhere to the UML definition: Only public operations as defined in the UML model are instrumented, whether those operations are implemented as public methods or not in the source code. This strategy is summarized in Table1 , which is adapted from [12]. Table 1.... In PAGE 9: ... Table1 also shows what is checked when an exception is thrown during the execution of a constrained method. A postcondition is not checked on abnormal termination of a method or constructor as the contract is likely not satisfied.... ..."