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Table 1: Hardware overheads

in On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers
by U. Sparmann, S. M. Reddy 1996
"... In PAGE 15: ... The results for a speci c architec- ture can be slightly better. Table1 summarizes the results obtained. The rst column speci es the bit width of the multiplier.... In PAGE 15: ...Table 1: Hardware overheads As can be observed from Table1 , the hardware overhead reduces by approximately one half when la- tency is allowed, and the duplication checks for the input registers and the recoder are omitted. Since for Booth recoded multiplication a larger amount of checking hardware can be omitted, the savings are slightly higher in this case.... In PAGE 15: ... In this situation the residue generation circuits could not be shared with other modules. But note that for this case the duplication of input registers can be saved, thus reducing the overhead numbers of Table1 for the no... In PAGE 16: ...ncoding, i.e. we assume the worst case where two residue code generation circuits are needed and their overhead can not be shared with other modules. The observations made for Table1 also apply here, i.e.... ..."
Cited by 2

TABLE V HARDWARE OVERHEAD FOR THE POLICIES

in This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. IEEE TRANSACTIONS ON COMPUTERS On-Demand Solution to Minimize I-Cache Leakage Energy with Maint
by Sung Woo Chung, Kevin Skadron

Table 1. Hardware overhead induced by an ICN.

in Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking On FPGAs
by Theodore Marescaux, Andrei Bartic, Diderick Verkest, D. Verkest, Rudy Lauwereins, Serge Vernalde, R. Lauwereins 2002
Cited by 24

Table 1: Experimental results: low hardware overhead.

in A Quantitative Approach to Functional Debugging
by Darko Kirovski, Miodrag Potkonjak 1997
"... In PAGE 4: ... 6 Experimental Results We applied the new design for debugging approachon several real-life designs #5B11#5D. Table1 shows the experimen- tal results. The #0Crst column indicates the name of the evaluated design.... ..."
Cited by 3

Table 6 Estimates of Hardware Overhead for Pseudorandom Testing

in 2004 Society for Design and Process Science Printed in the United States of America ALIASING-FREE COMPACTION IN TESTING CORES- BASED SYSTEM-ON-CHIP (SOC) USING COMPATIBILITY OF RESPONSE DATA OUTPUTS
by Sunil R. Das, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu

Table 3: Hardware Overhead for Our Scheme Modules Hardware

in Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier ∗
by Mahmut Yilmaz, Derek R. Hower, Sule Ozev, Daniel J. Sorin
"... In PAGE 8: ...3 Performance, Hardware, and Power Fault tolerant schemes incur hardware, performance, and power consumption overheads. Hardware: The details of the hardware overhead of our fault tolerant multiplier are in Table3 . The largest overhead is due to the reconfiguration logic which in- cludes the spare RU.... ..."

Table 4 Hardware overhead for the test generators for the circuits studied.

in Design of scalable hardware test generators for on-line
by Hussain Al-asaad 1996
"... In PAGE 3: ... For an n-bit carry-lookahead adder, the test generator requires n flip- flops and n cells of the linear array. The hardware overhead of the test generator is shown in Table4 . This overhead decreases as the number of bits of the carry-lookahead adder increases.... In PAGE 3: ... For an n-bit ALU, the test generator requires only n flip-flops with some constant logic independent of n. The hardware overhead of the test generator is shown in Table4 . This overhead decreases as the number of inputs of the ALU increases.... In PAGE 4: ... A pos- sible implementation of the resulting test generator is shown in Figure 5. The hardware overhead of the test generator is shown in Table4 . It decreases as n increases and amounts to 13.... ..."
Cited by 1

Table 6: Hardware overhead of the compactor with q = 1, and zero-aliasing

in Synthesis of Single-Output Space Compactors with Application to Scan-based IP Cores
by Bhargab B. Bhattacharya, Alexej Dmitriev, Bhargab B. Bhattacharya Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty 2002
"... In PAGE 6: ... For example, we partitioned the 320 functional out- puts of s35932 into 10 groups of 32 outputs each. The experimental results for zero-aliasing space com- paction are shown in Table6 . We report the hardware overhead for twocombinational and seven sequential circuits.... ..."
Cited by 2

Table 2 - Hardware overhead (2-input NAND gates)

in Self-Test Methodology for AtSpeed Test of Crosstalk
by Xiaoliang Bai 2000
"... In PAGE 5: ... We have synthesized the original DSP chip, as well as the chip with self-test structures inserted, using Mentor Graphics Leonardo synthesis tool [11]. Table2 shows the synthesis results, in terms of the number of 2-input NAND gates for each original component and after test structures are inserted. The total hardware overhead (measured in 2-input NAND gate) for the self- test methodology is about 22%.... In PAGE 5: ... The total hardware overhead (measured in 2-input NAND gate) for the self- test methodology is about 22%. As shown by Table2 , the high overhead is due to the relatively small size of some of the components (like PCU and the Bus Switch). We expect that the area overhead will be much smaller when we compare the area of the physical layouts of the original and final circuits, as this will consider the area due to the bus components, which constitute a significant part of the circuit, and for which there is no extra test overhead.... ..."
Cited by 20

Table 2 - Hardware overhead (2-input NAND gates)

in Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects
by X. Bai, S. Dey, J. Rajski, Xiaoliang Bai 2000
"... In PAGE 5: ... We have synthesized the original DSP chip, as well as the chip with self-test structures inserted, using Mentor Graphics Leonardo synthesis tool [11]. Table2 shows the synthesis results, in terms of the number of 2-input NAND gates for each original component and after test structures are inserted. The total hardware overhead (measured in 2-input NAND gate) for the self- test methodology is about 22%.... In PAGE 5: ... The total hardware overhead (measured in 2-input NAND gate) for the self- test methodology is about 22%. As shown by Table2 , the high overhead is due to the relatively small size of some of the components (like PCU and the Bus Switch). We expect that the area overhead will be much smaller when we compare the area of the physical layouts of the original and final circuits, as this will consider the area due to the bus components, which constitute a significant part of the circuit, and for which there is no extra test overhead.... ..."
Cited by 20
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