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Hardware Implementation of Communication Protocols
, 2000
"... In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of multi-way synchronization enables simple and comprehensible specifications of recent communication protocols which frequently ..."
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In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of multi-way synchronization enables simple and comprehensible specifications of recent communication protocols which
Firewall: Software and Hardware Implementations
"... Abstract A firewall is simply a program or hardware device that filters the information coming through the Internet connection into the private network or computer system. If an incoming packet of information is flagged by the filters, it is not allowed through. In this research paper we mainly foc ..."
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Abstract A firewall is simply a program or hardware device that filters the information coming through the Internet connection into the private network or computer system. If an incoming packet of information is flagged by the filters, it is not allowed through. In this research paper we mainly
Chapter 8 Hardware Implementation
"... In the classical Irradiance Caching algorithm, rays are first traced from the viewpoint towards the scene. For each corresponding intersection point, the irradiance cache is queried to determine whether a new irradiance record has to be created. When a new record is required, the irradiance value is ..."
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with the repeated branching inherent to recursive structures. Also, as pointers are not natively supported, the implementation of an unbalanced octree is not straightforward. To achieve a better efficiency, we reformulate the algorithm to fit to the computational model of graphics hardware: parallel computing
A Parallel Hardware Implementation
"... . This paper presents implementations of genetic algorithms in a tree shape parallel computer architecture. Different levels of parallelism involved in GAs are studied. In addition, basic models for parallel GAs are considered. The tree shape parallel computer system, GAPA (Genetic Algorithm Par ..."
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Parallel Accelerator), is described in detail, including architecture and special hardware for GA computations. Mapping studies are given for centralized and distributed GA models. Keywords: parallel GA, parallel implementation, parallel computer, tree shape architecture. 19.1 Introduction Genetic
An Efficient Hardware Implementation of the KASUMI
"... Third generation cellular network technology (3G) allows the transmission of information and voice at data rates never experienced before. 3G networks will revolutionize personal communications and information exchange between business partners in a more overwhelming fashion than 2G and 2.5 networks ..."
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FPGA implementation of KASUMI based on three design principles: the reuse of simple components to implement the whole cipher with fewer resources, the use of dual-port synchronous memories to implement the algorithm's substitution boxes (S-boxes), and the use of a simple key scheduler synchronized
Hardware Implementation of an SK Spectrometer
"... A wideband spectrometer of 500 MHz instantaneous bandwidth is described that includes an im-plementation of the Spectral Kurtosis (SK) algorithm for automatic radio frequency interference (RFI) detection. An SK spectrometer accumulates both power and power-squared, which are then used to develop the ..."
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A wideband spectrometer of 500 MHz instantaneous bandwidth is described that includes an im-plementation of the Spectral Kurtosis (SK) algorithm for automatic radio frequency interference (RFI) detection. An SK spectrometer accumulates both power and power-squared, which are then used to develop
Hardware Implementation of The Chameleon Polymorphic
, 2009
"... The Chameleon Cipher-192 is a polymorphic cipher that uses a variable word size and variable-size user’s key. The cipher employs a shuffler and two nonlinearity-associated filters for selective addition. The cipher structure is based on the simultaneous use of block and stream cipher approaches. Oth ..."
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established that the self-modifying proposed cipher, based on the aforementioned key-dependencies, provides an algorithm polymorphism and adequate security with a simple parallelizable structure. In this work, we provide an analysis of this cipher and an FPGA implementation.
Towards hardware implementation of loop subdivision
- In HWWS ’00: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware, ACM
"... We present a novel algorithm to evaluate and render Loop subdivision surfaces. The algorithm exploits the fact that Loop subdivision surfaces are piecewise polynomial and uses the forward difference technique for efficiently computing uniform samples on the limit surface. The main advantage of our a ..."
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Cited by 24 (1 self)
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algorithm is that it only requires a small and constant amount of memory that does not depend on the subdivision depth. The simple structure of the algorithm enables a scalable degree of hardware implementation. By low-level parallelization of the computations, we can reduce the critical computation costs
Results 11 - 20
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25,974
