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Table 2: Hardware implementation

in An Architecture for Accessible and Sharable Digital Video in the Home Environment
by unknown authors

Table 4: Hardware implementation costs.

in Cost Effective Fault Tolerance for Network Routing
by William Yost 1995
"... In PAGE 7: ...able 3: Maximum diameter of 2-dimensional mesh networks with random faults. ...... 39 Table4 : Hardware implementation costs.... ..."

Table 7. Evaluation of hardware implementation

in The block cipher SC2000
by Takeshi Shimoyama, Hitoshi Yanami, Kazuhiro Yokoyama, Masahiko Takenaka, Kouichi Itoh, Jun Yajima, Naoya Torii 2001
"... In PAGE 15: ... We note that the performance of the key schedule in our JAVA implementation is measured on the processing speed for swapping all the extended keys without re-construction of the structure of the encryption function. Table7 shows our evaluations in hardware implementations. There are three kinds of implementations, Large, Medium and Small.... ..."
Cited by 3

Table 1: Cost of hardware implementation

in A Formal Methodology for Hardware/Software Co-design of Embedded Systems
by Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto Sangiovanni-Vincentelli 1994
"... In PAGE 19: ...The synthesis system described in this paper produced various choices of implementation for each CFSM. Table1 describes the cost of a hardware im- plementation of each CFSM (separately optimized) in terms of square microns in a 3 m technology. The delay of this implementation is almost negligible, and is supposed to be the same as the clock cycle of the micro-controller (a reasonable choice in an embedded system).... ..."
Cited by 15

Table 10: Summary of hardware implementations

in Contents Self Evaluation: Hierocrypt–3 Toshiba Corporation
by unknown authors 2000

TABLE I HARDWARE IMPLEMENTATION RESULTS

in A High-Speed Hardware Implementation of the LILI-II Keystream Generator
by P. Kitsos, N. Sklavos, O. Koufopavlou

Table 7. Statistics of the hardware implementations.

in Efficient Memory Management for High-Speed ATM Systems
by D. N. Serpanos

Table 2. FPGA Hardware implementation results

in An Approach to full User Data Integrity Protection in UMTS Access Networks
by unknown authors
"... In PAGE 9: ... The idea for table 1 is to provide a relative comparison in each column. Table2 contains values used for relative performance comparison of hardware implementations of the solutions. An ideal comparison would require one research in which all of our candidates were tested with comparable optimizations in the implementation and on identical devices.... ..."

Table 1. Compact hardware implementations of AES

in Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks
by Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen
"... In PAGE 4: ... Whereas earlier AES designs mainly focused on intensively pipelined, high-speed implementations, the more recent work has concentrated on compactness and lower power consumption. Of all the de- signs, Table1 lists the proposals which we have considered to have achieved the most significant results and which are possibly suitable for highly resource-constrained WSN nodes. The table is organized according to the time of publication of the designs, in or-... ..."

Table II. Parameters of SBC hardware implementation

in An Efficient Single-Pass Trace Compression Technique Utilizing Instruction Streams
by Aleksandar Milenković, Milena Milenković 2007
Cited by 1
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