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393
Calculus of Bargaining Solution on Boolean Tables
, 2003
"... This article reports not only a theoretical solution of bargaining problem as used by game theoreticians but also an adequate calculus. By adequate calculus we understand an algorithm that can lead us to the result within reasonable timetable using either the computing power of nowadays computers or ..."
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or widely accepted classical Hamiltonian method of function maximization with constraints. Our motive is quite difficult to meet but we hope to move in this direction in order to close the gap at least for one nontrivial situation on Boolean Tables.
Efficient implementation of a BDD package
 In Proceedings of the 27th ACM/IEEE conference on Design autamation
, 1991
"... Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient implementat ..."
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Cited by 504 (9 self)
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Efficient manipulation of Boolean functions is an important component of many computeraided design tasks. This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation. The package is based on an efficient
Compiling Logical Features into Specialized StateEvaluators by Partial Evaluation, Boolean Tables and Incremental Calculation
, 2000
"... . A good evaluation function is needed for a good game program, and good features, which are primitive metrics of a state, are needed for a good evaluation function. In order to obtain good features, automatic generation of features by machine learning is promising. However, the generated featur ..."
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: partial evaluation, Boolean tables, and incremental calculation. It exhaustively unfolds logical programs until they can be represented as simple Boolean tables. The constructed specialized evaluator is ecient since it consults only these compiled tables. Experiments with Othello showed that speed can
FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in LookupTable Based FPGA Designs
 IEEE TRANS. CAD
, 1994
"... The field programmable gatearray (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookuptable (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Bo ..."
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Cited by 321 (41 self)
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The field programmable gatearray (FPGA) has become an important technology in VLSI ASIC designs. In the past a few years, a number of heuristic algorithms have been proposed for technology mapping in lookuptable (LUT) based FPGA designs, but none of them guarantees optimal solutions for general
Reveal, A General Reverse Engineering Algorithm For Inference Of Genetic Network Architectures
, 1998
"... Given the immanent gene expression mapping covering whole genomes during development, health and disease, we seek computational methods to maximize functional inference from such large data sets. Is it possible, in principle, to completely infer a complex regulatory network architecture from input/o ..."
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Cited by 344 (5 self)
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/output patterns of its variables? We investigated this possibility using binary models of genetic networks. Trajectories, or state transition tables of Boolean nets, resemble time series of gene expression. By systematically analyzing the mutual information between input states and output states, one is able
IDENTIFICATION OF GENETIC NETWORKS FROM A SMALL NUMBER OF GENE EXPRESSION PATTERNS UNDER THE BOOLEAN NETWORK MODEL
 PACIFIC SYMPOSIUM ON BIOCOMPUTING 4:1728 (1999)
, 1999
"... ... for inferring genetic network architectures from state transition tables which correspond to time series of gene expression patterns, using the Boolean network model. Their results of computational experiments suggested that a small number of state transition (INPUT/OUTPUT) pairs are sufficient ..."
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Cited by 254 (17 self)
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... for inferring genetic network architectures from state transition tables which correspond to time series of gene expression patterns, using the Boolean network model. Their results of computational experiments suggested that a small number of state transition (INPUT/OUTPUT) pairs are sufficient
Decomposition of probability tables representing Boolean functions
"... We apply tensor rankone decomposition (Savicky and Vomlel, 2005) to conditional probability tables representing Boolean functions. We present a numerical algorithm that can be used to find a minimal tensor rankone decomposition together with the results of the experiments performed using the propo ..."
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We apply tensor rankone decomposition (Savicky and Vomlel, 2005) to conditional probability tables representing Boolean functions. We present a numerical algorithm that can be used to find a minimal tensor rankone decomposition together with the results of the experiments performed using
Decomposition of Probability Tables Representing Boolean Functions
"... We apply tensor rankone decomposition (Savicky and Vomlel, 2005) to conditional probability tables representing Boolean functions. We present a numerical algorithm that can be used to find a minimal tensor rankone decomposition together with the results of the experiments performed using the propo ..."
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We apply tensor rankone decomposition (Savicky and Vomlel, 2005) to conditional probability tables representing Boolean functions. We present a numerical algorithm that can be used to find a minimal tensor rankone decomposition together with the results of the experiments performed using
On TruthTable Reducibility to SAT
, 2002
"... We show that polynomial time truthtable reducibility via Boolean circuits to SAT is the same as logspace truthtable reducibility via Boolean formulas to SAT and the same as logspace Turing reducibility to SAT . In addition, we prove that a constant number of rounds of parallel queries to SAT i ..."
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Cited by 52 (2 self)
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We show that polynomial time truthtable reducibility via Boolean circuits to SAT is the same as logspace truthtable reducibility via Boolean formulas to SAT and the same as logspace Turing reducibility to SAT . In addition, we prove that a constant number of rounds of parallel queries to SAT
Boolean Routing on Cayley Networks
, 1997
"... We study Boolean routing on Cayley networks. Let K(MG ) denote the Kolmogorov complexity of the multiplication table of a group G of order n. We show that O(maxfd log n; K(MG )g) memory bits per local router (hence a total of O(nmaxfd log n; K(MG )g) memory bits) are sufficient to do Boolean routin ..."
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Cited by 5 (3 self)
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We study Boolean routing on Cayley networks. Let K(MG ) denote the Kolmogorov complexity of the multiplication table of a group G of order n. We show that O(maxfd log n; K(MG )g) memory bits per local router (hence a total of O(nmaxfd log n; K(MG )g) memory bits) are sufficient to do Boolean
Results 1  10
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393