Results 11 - 20 of 12,196

Table 1: Hardware overhead for the proposed output data compressor.

in Selfadjusting output data compression: An efficient BIST technique for RAMs
by V. N. Yarmolik 1998
"... In PAGE 5: ... . 1 EXOR-gates, and 1 AND-gate. Table1 summarizes the hardware cost for some example configurations of word-... ..."
Cited by 2

Table 1: Area, speed, hardware overhead and reconfigurability of different adders.

in Techniques for Yield Enhancement of VLSI Adders 1
by Zhan Chen, Israel Koren

Table 2: DFT hardware placement overheads.

in A Design for Testability Technique for RTL Circuits Using Control/Data Flow Extraction
by Indradeep Ghosh, Niraj K. Jha 1996
"... In PAGE 7: ... The number of test multiplexers added to the circuit by the DFT procedure is given in Column 5. This number does not include the multiplexers in the test architecture which are added by de- fault to all circuits, and which have been taken into account while calculating the overheads in Table2 . In Column 6, the CPU time required to extract the TCDF and place the DFT hardware is given.... In PAGE 7: ... All CPU times are measured on a SPARCstation 20 with 128 MB memory. In Column 2 of Table2 the original area of the circuits after technol- ogy mapping is given. This is a relative figure obtained from the layouts of the standard cells used and hence has no units.... ..."
Cited by 13

Table 3: DFT hardware placement overheads

in unknown title
by unknown authors 1998
"... In PAGE 10: ...sists of the number of extra multiplexers in the data path and does not include the multiplexers used for testing the controller which are added by default to all circuits [4, 5], and which have been in- cluded while reporting the overheads in Table 3. Table3 shows the area and delay overheads for our DFT scheme. In Column 2, the original technology-mapped area of the circuits is given.... ..."
Cited by 8

Table 3. Hardware and Power Overheads for Multiplier

in unknown title
by unknown authors 2007
"... In PAGE 8: ...most benchmarks, we could tolerate even lazier checkers with little impact, but some floating point benchmarks see non-trivial performance loss once C reaches 10. As can be seen in Table3 , the modulo checker is only one-tenth the size of the primary 4- cycle multiplier. This shows that the checker itself is low-cost in terms of hardware.... ..."
Cited by 1

Table 2: DFT hardware placement overheads

in Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs
by Indradeep Ghosh Anand, Niraj K. Jha 1997
"... In PAGE 6: ... From Column 5 it is clear that the test microcode is usually successful in eliminating the need of test multiplexers from the data path except for some unavoidable cases, as discussed in Section 2. Table2 shows the area and delay overheads for our DFT scheme. In Column 2 the original technology- mapped area of the circuits is given.... ..."
Cited by 4

Table 2: DFT hardware placement overheads

in Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs
by Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha 1997
"... In PAGE 6: ... From Column 5 it is clear that the test microcode is usually successful in eliminating the need of test multiplexers from the data path except for some unavoidable cases, as discussed in Section 2. Table2 shows the area and delay overheads for our DFT scheme. In Column 2 the original technology- mapped area of the circuits is given.... ..."
Cited by 4

Table 2: DFT hardware placement overheads

in A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis
by Indradeep Ghosh, Nirajk Jha, Sudipta Bhawmik, Indradeepghosh Nirajk, Jha Sudiptabhawmik
"... In PAGE 5: ... Table 1 shows the characteristics and specifications of these cir- cuits. The BIST overheads are reported in Table2 and the testabil- ity results are shown in Figure 10. In Table 1, Column 2 shows the bit-width of the circuit data paths.... In PAGE 5: ... This is a major advantage over many previous testability analysis schemes [5] where the CPU time for analysis explodes with an increase in the data path bit-width. In Column 2 of Table2 , the original area of the circuits after technology mapping is given. This is a relative figure obtained from the layouts of the standard cells used, and hence has no units.... ..."

Table 2: DFT hardware placement overheads

in ABISTSchemeforRTLController-DataPathsBasedonSymbolic
by Indradeepghosh Nirajk, Jha Sudiptabhawmik
"... In PAGE 5: ... Table 1 shows the characteristics and specifications of these cir- cuits. The BIST overheads are reported in Table2 and the testabil- ity results are shown in Figure 10. In Table 1, Column 2 shows the bit-width of the circuit data paths.... In PAGE 5: ... This is a major advantage over many previous testability analysis schemes [5] where the CPU time for analysis explodes with an increase in the data path bit-width. In Column 2 of Table2 , the original area of the circuits after technology mapping is given. This is a relative figure obtained from the layouts of the standard cells used, and hence has no units.... ..."

Table 2. Hardware and Power Overheads for Adder

in unknown title
by unknown authors 2007
"... In PAGE 7: ...Table2 , the adder checker is inexpensive. In total, it uses 1108 transistors, which is 32% the size of the primary adder and far less than replication.... ..."
Cited by 1
Results 11 - 20 of 12,196