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Table 1: Comparison of Digital Hardware Implementations DEVICE Number

in RF SYSTEM DEVELOPMENT FOR THE CEBAF ENERGY UPGRADE*
by C. Hovater, P. Chevtsov, J. Delayen, H. Dong, L. Harwood, J. Musson, R. Nelson
"... In PAGE 3: ... We compared each hardware implementation using the same logic function block shown in figure 4. FIR 10 Tap Rotation Matrix I amp;Q Set Point Feed Forward PID Loop PID Loop FIR 10 Tap Scaling Scaling I Input Q Input I out Q Out To DAC From ADC Digital Down Converter Reference Clock Figure 4: LLRF Logic Functions Table1 is a comparison of the three different hardware implementations for digital feedback. As is industry, we are also investigating programmable gate arrays with DSP block sets.... ..."

Table 19: Previous Implementations in Hardware

in unknown title
by unknown authors 2003
"... In PAGE 44: ...1.1 Previous Results Table19 lists known implementations external to the NESSIE project. For block ciphers, the quoted results apply to encryption without key schedule.... ..."

Table III. HW/SW features for the operations that candidate for hardware implementation

in The molen compiler for reconfigurable processors
by Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis, Tu Delft 2007
Cited by 7

Table 2. Exact operation sequence of our hardware implementation of formula (8)

in Area efficient hardware implementation of elliptic curve cryptography by iteratively applying karatsuba’s method
by Zoya Dyka, Peter Langendoerfer 2005
Cited by 5

Table V-2. Results from Cantata and Hardware Implementations of START.

in A System for the Implementation of Image Processing Algorithms on Configurable Computing Hardware
by Benjamin Alexander Levine 1999
Cited by 2

Table 3. Performance Comparison for Test Problems Hardware Implementations

in FPGA-based high-order finite difference algorithm for 2D acoustic wave propagation problems
by Chuan He, Wei Zhao, Mi Lu 2005
Cited by 1

TABLE 2. The hardware implementation counts of the three architectural candidates.

in A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction
by Jaesung Lee, Hyuk-jae Lee, Chanho Lee 2007

TABLE I LOGIC-ENHANCED MEMORY HARDWARE IMPLEMENTATION RESULTS

in Efficient Hardware for Tile-Based Rasterization
by Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha

Table 1: Classi cation of hardware-implemented TPG methods.

in On-Chip Test Generation Using Linear Subspaces Abstract
by Ramashis Das, Igor L. Markov, John P. Hayes

Table 3. Hardware modules to implement functions.

in An Evolutionary Approach to Hardware/Software Partitioning
by Xiaobo Sharon Hu, Garrison Greenwood, Joseph G. D'Ambrosio 1996
"... In PAGE 8: ... The #0Crst 4 functions may be implemented in hardware. Table3 lists some of the hardware modules available for this system. The modules include: microcontrollers #28MC#29, processors #28P#29, ASICs, standard peripherals #28PIO#29, timing channels #28TC#29, RAM,... ..."
Cited by 7
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