Abstract:
This paper introduces a new technique for power estimation; one which can account accurately for nearly all power-dissipating events in a circuit, including spurious pulses. The main idea is to represent circuit operation by a directed graph, called the circuit transition graph, such that there is a one-to-one correspondence between edges in the graph and power-dissipating events in the circuit. The method appears to be particularly applicable to latch design. Using it we derive analytical formulas expressing latch power in terms of true and spurious switching activities at the latch input. These formulas are then applied to a wide variety of commonly used latch designs, and verified through analog simulation. Given the importance of latches to real digital systems, these results will allow designer to approach the process of optimizing power efficiency in a formal and rigorous fashion.
Citations
|
182
|
A Survey of Power Estimation Techniques in VLSI Circuits
– Najm
- 1994
|
|
120
|
Transition density: a new measure of activity in digital circuits
– Najm
- 1993
|
|
82
|
McPower: A monte carlo approach to power estimation
– Burch, Najm, et al.
- 1992
|
|
67
|
and Christer Svensson. High-speed CMOS circuit technique
– Yuan
- 1989
|
|
55
|
Probabilistic simulation for reliability analysis
– Najm, Burch, et al.
- 1990
|
|
50
|
Exact and approximate methods for calculating signal and transition probabilities in FSMs
– Tsui, Pedram, et al.
- 1994
|
|
31
|
Power estimation in sequential logic circuits
– Tsui, Monteiro, et al.
- 1995
|
|
25
|
HEAT: Hierarchical Energy Analysis Tool
– Satyanarayana, Parhi
- 1996
|
|
17
|
Low-pass filter for computing the transition density in digital circuits
– Najm
- 1994
|
|
15
|
The design of a high performance low power microprocessor
– Dobberpuhl
- 1996
|
|
14
|
Power estimation techniques for integrated circuits
– NAJM
- 1995
|
|
12
|
Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation
– Monteiro, Devadas, et al.
- 1997
|
|
8
|
Correlation and Delay Concerns in the Power Estimation of VLSI Circuits
– Najm
- 1995
|
|
7
|
et al. "A 200-MHz 64-bit Dual-Issue CMOS Microprocessor
– Dobberpuhl
- 1992
|
|
7
|
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine
– Hachtel, Macii, et al.
- 1994
|
|
2
|
Energy-recovery CMOS," in Low Power Design Methodologies
– Athas
- 1995
|
|
2
|
et al., "Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU
– Bowhill
- 1995
|
|
2
|
The Microprogramming of Pipelined
– Kogge
- 1977
|
|
1
|
Logic synthesis for low power." In: Low Power Design Methodologies
– Pedram
- 1996
|
|
1
|
Low power circuit techniques." In: Low Power Design Methodologies
– Svensson, Liu
- 1996
|
|
