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by Member Ieee, Philip N. Strenski, Philip G. Emma
http://www.eecs.harvard.edu/~dbrooks/toc_pipeline.pdf
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Abstract:
Abstract—Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a microprocessor design. To be successful in today’s cost/performance marketplace, modern CPU designs must effectively balance both performance and power dissipation. The choice of pipeline depth and target clock frequency has a critical impact on both of these metrics. In this paper, we describe an optimization methodology based on both analytical models and detailed simulations for power and performance as a function of pipeline depth. Our results for a set of SPEC2000 applications show that, when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of our energy models. Finally, we discuss the potential risks in design quality for overly aggressive or conservative choices of pipeline depth. Index Terms—Low-power design, energy-aware systems, pipeline processors, performance analysis and design aids, microprocessors and microcomputers. 1
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received the BS
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received the BS
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received the BS degree in physics from the University of Madras in 1990, the MS degree in computer science and engineering from the Indian Institute of Science in 1994, and the PhD degree in computer science and engineering from the University
– Srinivasan
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1
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received the MS and PhD degrees in computer science from the Technische Universität Wien in 1991 and 1996, respectively. He is a research staff member at the IBM T.J. Watson Research Center. He was one of the originators of the supercomputer-ona-chip “Cel
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received the BTech (Hons.) degree from I.I.T
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- 1983
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Strenski received the AB degree in mathematics in 1979 from Washington University and the PhD degree in physics in 1985 from Stanford University. That same year he joined IBM, engaging in research in design automation, including simulated annealing, param
– Philip
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