Performance modeling of multithreaded distributed memory architectures (1999) [2 citations — 1 self]
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by W. M. Zuberek
Proc. 2-nd Workshop on hardware Design and Petri Nets
ftp://ftp.cs.mun.ca/pub/publications/99-HWPN.ps.Z
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Abstract:
Abstract. In multithreaded distributed memory architectures, long--latency memory operations and synchronization delays are tolerated by suspending the current thread and switching to another thread, which is executed concurrently with the long--latency operation of the suspended thread. Timed Petri nets are used to model several multithreaded architectures at the instruction and thread levels. Model evaluation results are presented to illustrate the influence of different model parameters on the performance of the system. 1
Citations
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