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by Yervant Zorian, Erik Jan Marinissen, Sujit Dey
In Proceedings IEEE International Test Conference (ITC
http://esdat.ucsd.edu/dey/papers/itc98-zorian.ps
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Abstract:
Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design, in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research. 1
Citations
|
98
|
A Distributed BIST Control Scheme for Complex VLSI Devices
– Zorian
- 1993
|
|
55
|
Scan Chain Design for Test Time Reduction in Core-Based ICs
– Aerts, Marinissen
- 1998
|
|
38
|
Direct Access Test Scheme- Design of Block and Core Cells for Embedded ASICs
– Immaneni, Raman
- 1990
|
|
33
|
Test requirements for embedded core-based systems and
– Zorian
- 1997
|
|
30
|
A Low Overhead Design for Testability and Test Generation Technique for Core-based Systems-on-a-Chip
– Gosh, Jha, et al.
- 1999
|
|
23
|
A fast and low cost testing technique for core-based system-chips
– Ghosh, Jha
- 2000
|
|
23
|
IEEE 1149.1 based test access architecture for ICs with embedded cores
– Whetsel
- 1997
|
|
17
|
Defect Detection with Transient Current Testing and Its Potential for Deep Submicron ICs
– Sachdev, Zieren, et al.
- 1998
|
|
14
|
A Simplified Polynomial-Fitting Algorithm for
– Sunter, Nagi
- 1997
|
|
10
|
and Yervant Zorian. Introducing Core-Based System Design
– Gupta
- 1997
|
|
10
|
Hierarchical test access architecture for embedded cores in an integrated circuit
– Bhattacharya
- 1998
|
|
9
|
Modifying User-Defined Logic for Test Access to Embedded Cores
– Pouya, Touba
- 1997
|
|
9
|
Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores
– Jan
- 1998
|
|
8
|
Built-In Self-Test for Digital Integrated Circuits
– Agrawal, Lin, et al.
- 1994
|
|
7
|
Macro Test: A Liberal Test Approach for Embedded Reusable Cores
– Marinissen, Lousberg
- 1997
|
|
7
|
Macro Testability: the results of production device applications
– Bouwman, Oostdijk, et al.
- 1992
|
|
6
|
Modular logic built-in self-test for IP cores
– Rajski, Tyszer
- 1998
|
|
5
|
A Structured Test Re-Use Methodology for Systems on Silicon
– Varma, Bhatia
- 1997
|
|
5
|
Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms
– Taylor, Maston
- 1996
|
|
4
|
Scan-Based BIST with Complete Fault Coverage and Low Hardware Overhead
– Wunderlich, Kiefer
- 1996
|
|
3
|
et al. Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
– Nordholz
- 1998
|
|
3
|
A general purpose Iddq measurement circuit
– Wallquist, Righter, et al.
- 1993
|
|
2
|
Loek Thijssen. Testability Concepts for Digital ICs - The Macro Test Approach
– Beenker, Bennetts
- 1995
|
|
2
|
Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach
– Feige, Pierick, et al.
- 1998
|
|
1
|
Synthesising processors
– Jani, Acken
- 1995
|
|
1
|
A General Purpose I DDQ Measurement Circuit
– Wallquist, Righter, et al.
- 1993
|
|
1
|
A 2-Step Strategy tackles System-on-a-Chip Test
– Zorian, Chandramouli
- 1997
|
|
1
|
Core Provider's Test Experience. http://grouper.ieee.org/groups/1500/pastmeetings.html#dac98. Presentation at
– Mathewson
- 1998
|
|
1
|
Evolving Strategies for Testing Systems on Silicon
– Varma
- 1997
|
|
1
|
Debugging Embedded Systems. http://www.arm.com/Documentation/WhitePapers/DebugEmbSys
– Goudge
|
