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  The Reduction of Test-Time in VLIW-TTA Processors

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by Vladimir A. Zivkovic, Hans G. Kerkhoff, Ronald J. W. T. Tangelder
http://www.stw.nl/programmas/prorisc/proc2000/../proc-2001/zivkovic.pdf
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Abstract:

Abstract – In this paper the implementation of the test

Citations

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1 DfT and BIST Techniques for the MOVE Architecture,” M.Sc Assignment – Hoek - 1999
1 Computer-Aided Test Flow in Core-Based Design – Zivkovic, Kerkhoff
1 An Implementation for Test-Time Reduction – Zivkovic, Tangelder, et al.