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  \Sigma 1) Addition and Multiplication

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by Reto Zimmermann
http://www.stud.ee.ethz.ch/~zimmi/publications/modulo_arith.ps.gz
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Abstract:

New VLSI circuit architectures for addition and multiplication modulo (2 n

Citations

222 Parallel prefix computation – Ladner, Fischer - 1980
171 Computer Arithmetic Algorithms – Koren - 1993
113 Massey “ A proposal for a new Block Encryption Standard – Lai, L
26 A Reduced-Area Scheme for Carry-Select Adders – Tyagi - 1993
20 Binary Adder Architectures for Cell-Based VLSI and their Synthesis – Zimmermann - 1248
16 Regular VLSI architecture for multiplication modulo (2 n +1 – Curiger, Bonnenberg, et al. - 1991
13 Non-heuristic optimization and synthesis of parallel-prefix adders – Zimmermann - 1996
12 A VLSI Implementation of Residue Adders – Bayoumi, Jullien, et al. - 1987
9 VHDL Library of Arithmetic Units – Zimmermann
7 A Simplified Architecture for Modulo (2 n + 1) Multiplication – Ma - 1998
4 An efficient tree architecture for modulo 2 n +1 multiplication – Wang, Jullien, et al. - 1996
3 Modulo (2 n + 1) arithmetic logic – Agrawal, Rao - 1978
3 New memoryless, mod (2 n \Sigma1) residue multiplier – Hiasat - 1992
2 Area-time efficient modulo 2 n \Gamma 1 adder design – Efstathiou, Nikolos, et al. - 1994
2 New multipliers modulo 2 n \Gamma 1 – Skavantzos, Rao - 1992
2 Modulo 2 p \Gamma 1 arithmetic hardware algorithm using signed-digit number representation – Wei, Shimizu - 1996