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Abstract: The Network-on-Chip architecture and design methodology aims at providing a communication backbone for on-chip communication which can cope with the complexity of future System-on-Chip designs. Given the high number of resources and applications in a NoC, di#erent communication streams will have di#erent Quality-of-Service requirements (characterised by parameters like bandwidth, error probability etc.). (Update)
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BibTeX entry: (Update)
Zimmer, H.: Fault modelling and error-control coding in a network-onchip. Master's thesis, Laboratory of Electronics and Computer Systems, Royal Institute of Technology (KTH), IMIT/LECS 2002-26, Stockholm, 2002 http://citeseer.ist.psu.edu/zimmer02fault.html More
@misc{ zimmer02fault,
author = "H. Zimmer",
title = "Fault modelling and error-control coding in a network-onchip",
text = "Zimmer, H.: Fault modelling and error-control coding in a network-onchip.
Master's thesis, Laboratory of Electronics and Computer Systems, Royal Institute
of Technology (KTH), IMIT/LECS 2002-26, Stockholm, 2002",
year = "2002",
url = "citeseer.ist.psu.edu/zimmer02fault.html" }
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