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by Craig Zilles, Gurindar Sohi
http://www.cs.wisc.edu/~zilles/papers/mssp.micro2002.ps
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Abstract:
Master/Slave Speculative Parallelization (MSSP) is an execution paradigm for improving the execution rate of sequential programs by parallelizing them speculatively for execution on a multiprocessor. In MSSP, one processor---the master---executes an approximate version of the program to compute selected values that the full program's execution is expected to compute. The master's results are checked by slave processors that execute the original program. This validation is parallelized by cutting the program's execution into tasks. Each slave uses its predicted inputs (as computed by the master) to validate the input predictions of the next task, inductively validating the entire execution. The performance of MSSP is largely determined by the execution rate of the approximate program. Since approximate code has no correctness requirements (in essence it is a software value predictor), it can be optimized more effectively than traditionally generated code. It is free to sacrifice correctness in the uncommon case to maximize performance in the common case. A simulation-based evaluation of an initial MSSP implementation achieves speedups of up to 1.7 (harmonic mean 1.25) on the SPEC2000 integer benchmarks. Performance is currently limited by the effectiveness with which our current automated infrastructure approximates programs, which can likely be improved significantly.
Citations
|
1253
|
The Simplescalar toolset, version 2.0
– Burger, Austin
- 1997
|
|
560
|
Trace scheduling: A technique for global microcode compaction
– Fisher
- 1981
|
|
313
|
The Alpha 21264 microprocessor
– Kessler
- 1991
|
|
213
|
The superblock: an effective technique for vliw and superscalar compilation
– Hwu, Mahlke, et al.
- 1993
|
|
177
|
DIVA: A Reliable Substrate for Deep Submicron
– Austin
- 1999
|
|
119
|
Data Speculation Support for a Chip Multiprocessor
– Hammond, Willey, et al.
- 1998
|
|
110
|
Slipstream Processors: Improving both Performance and Fault Tolerance
– Sundaramoorthy, Purser, et al.
- 2000
|
|
108
|
The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation
– Tsai, Yew
- 1996
|
|
100
|
Execution-based Prediction Using Speculative Slices
– Zilles, Sohi
- 2001
|
|
71
|
Architectural Support for Scalable Speculative Parallelization in SharedMemory Multiprocessors
– Cintra, Martínez, et al.
- 2000
|
|
63
|
Value profiling and optimization
– Calder, Feller, et al.
- 1999
|
|
31
|
A Dynamic Multithreading
– Akkary, Driscoll
|
|
29
|
Value prediction for speculative multithreaded architectures
– Marcuello, Tubella, et al.
- 1999
|
|
17
|
Transparent Dynamic Optimization
– Bala, Duesterwald, et al.
- 1999
|
|
9
|
Master/Slave Speculative Parallelization and Approximate Code
– Zilles
- 2002
|
|
7
|
et al. Performance Characterization of a Hardware Framework for Dynamic Optimization
– Fahs
- 2001
|
|
6
|
et al. Speculative precomputation: Longrange prefetching of delinquent loads
– Collins
- 2001
|
|
4
|
et al., “Dynamic Memory Disambiguation Using the Memory Conflict Buffer
– Gallagher
- 1994
|
|
4
|
et al. Improving Value Communication for Thread-Level Speculation. HPCA-6
– Steffan
- 2000
|
|
3
|
et al. Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading
– Dubey
- 1995
|
|
2
|
Dynamic Instruction Reuse. ISCA-24
– Sodani, Sohi
- 1997
|
