On Retargeting with FPGA Technology
by Zeljko Zilic, Zvonko Vranesic
http://www.eecg.toronto.edu/~zeljko/rtrgt.ps.Z
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Abstract:
The paper describes the experience and presents the results of a retargeting exercise aimed at replacing the PAL-implemented control circuitry of a high-performance multiprocessor with FPGA devices. While straightforward retargeting is easy to perform, it does not give good results with respect to speed requirements. In order to attain the desired speed performance, it is necessary to redesign the sequential circuits found in the original design.
Citations
| 33 | Mustang: State assignment of finite state machines for optimal multi-level logic implementations – Devadas, Ma, et al. - 1987 |
| 12 | Hector: A Hierarchically Structured Shared Memory Multiprocessor – Vranesic, Stumm, et al. - 1991 |
| 6 | Accelerate FPGA Macros with One-Hot Approach – Knapp - 1990 |
| 5 | Digital Systems Design with Programmable Logic – Bolton - 1990 |
| 3 | Guest Editors’ Introduction: New VLSI – Gajski, Kuhn - 1983 |
| 1 | Exemplar Logic – Manual - 1992 |

