(Enter summary)
Abstract: In this paper, we develop a formal framework to widen the
scope of retargetable compilation. The goal is achieved by the
unification of architectural models for both the processor architecture
and the ASIC architecture. This framework enables the
unified treatment of code generation and behavioral synthesis, and
is being used in our experimental codesign environment to drive
system-on-a-chip synthesis from an object oriented language.
1 Introduction
For billion-transistor chip design,... (Update)
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BibTeX entry: (Update)
J. Zhu, D.D. Gajski. A Unified Formal Model of ISA and FSMD. Technical Report ICS-98-44, University of California, Irvine. http://citeseer.ist.psu.edu/zhu95unified.html More
@inproceedings{ zhuunified,
author = "J. Zhu and D. D. Gajski",
title = "A Unified Formal Model of {ISA} and {FSMD}",
pages = "121--125",
url = "citeseer.ist.psu.edu/zhu95unified.html" }
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A Unified Formal Model of ISA and FSMD
- Zhu, Gajski
Documents on the same site (http://www.ics.uci.edu/~cad/publications/conferences/1995-99/INDEX.html): More
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