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Abstract: The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow memory operations such as cache misses) significantly. Therefore, for memory intensive workloads, it becomes more important to overlap multiple cache misses than to overlap slow memory operations with other computations. In this paper, we propose a novel technique to parallelize sequential cache misses, thereby increasing... (Update)
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0.1: Appears in the 11 - Th International Conference (Correct)
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BibTeX entry: (Update)
@misc{ zhou-enhancing,
author = "Huiyang Zhou and Thomas M. Conte",
title = "Enhancing Memory Level Parallelism via Recovery-Free Value Prediction",
url = "citeseer.ist.psu.edu/zhou03enhancing.html" }
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