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by Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte
http://www.tinker.ncsu.edu/symposia/lcpc01.ps
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Abstract:

Global scheduling in a treegion framework has been proposed to exploit instruction level parallelism (ILP) at compile time. A treegion is a single-entry / multiple-exit global scheduling scope that consists of basic blocks with control-flow that forms a tree. Because a treegion scope is nonlinear (includes multiple paths) it is distinguished from linear scopes such as traces or superblocks. Treegion scheduling has the capability of speeding up all possible paths within the scheduling scope. This paper presents a new global scheduling algorithm using treegions called Tree Traversal Scheduling (TTS). Efficient, incremental data-flow analysis in support of TTS is also presented. Performance results are compared to the scheduling of the linear regions that result from the decomposition of treegions. We refer to these resultant linear regions as linear treegions (LT) and consider them analogous to superblocks with the same amount of code expansion as the base treegion. Experimental results for TTS scheduling show a 35 % speedup compared to basic block (BB) scheduling and a 4 % speedup compared to LT scheduling. 1.

Citations

560 Trace scheduling: A technique for global microcode compaction – Fisher - 1981
134 Highly Concurrent Scalar Processing – Hsu - 1986
92 HPL PlayDoh Architecture Specification: Version 1.0 – Kathail, Schlansker, et al. - 1994
44 Percolation scheduling: A parallel compilation technique – Nicolau - 1985
43 HPL-PD architecture specification: Version 1.1 – Kathail, Schlansker, et al. - 2000
40 EPIC: Explicitly Parallel Instruction Computing – Schlansker, Rau
32 Exploiting Instruction Level Parallelism in the Presence of Conditional Branches – Mahlke - 1995
31 Treegion scheduling for wide-issue processors – Havanki, Banerjia, et al. - 1998
28 Profile-Driven Instruction Level Parallel Scheduling with Applications to Super Blocks – CHEKURI, JOHNSON, et al. - 1996
21 Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs – Bharadwaj, Menezes, et al. - 1999
19 Treegion scheduling for highly parallel processors – Havanki, Conte - 1997
19 Speculative Hedge: Regulating Compile-Time Speculation Against Profile Variations – DEITRICH, W-M - 1996
15 Elcor’s Machine Description System: Version 3.0 – Aditya, Kathail, et al. - 1998
11 Architectural support for compile-time speculation – Smith - 1994
10 Path prediction for high issue-rate processors – Menezes, Sathaye, et al. - 1997
10 Dynamic Branch Prediction for a VLIW Processor – Hoogerbrugge - 1997
9 The Superblock: An effective way for VLIW and superblock compilation.” The – Hwu, Mahlke, et al. - 1993
7 Sathaye, "Instruction fetch mechanisms for VLIW architectures with compressed encodings – Conte, Banerjia, et al. - 1996
3 Global code generation for instruction level parallelism – Fisher - 1993
2 Bringmann "Effective compiler support for predicated execution using the Hyperblock – Mahlke, Lin, et al. - 1992