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by Bin Zhou, Tomohiro Yoneda, Chris Myers
TIT CS Technical Report
ftp://ftp.cs.titech.ac.jp/pub/TR/01/TR01-0015.pdf
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Abstract:
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.
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