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Abstract: This thesis presents a framework for the specification and compilation of modules in a system that uses different synchronization paradigms. These timed systems are described by using timed handshaking expansions (HSE) and a standard hardware description language, namely VHDL. Synthesizable subsets of these languages are defined to include constructs for describing timing behaviors, as well as, sequencing, concurrency, choice and looping. A new formal semantic model, timed event/level... (Update)
Context of citations to this paper: More
.... latency penalty in globally synchronous systems [24] We are also designing a complete CAD system for timed circuit design [25] 26] [27], and are working on Design for Testability (DfT) solutions for the undetectable faults in self timed circuits. Such CAD and design...
.... penalty in globally synchronous systems [24] We are also designing a complete CAD system for timed circuit design [25] 26] 27] [28], and are working on Design for Testability (DfT) solutions for the undetectable faults in self timed circuits. Such CAD and design...
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BibTeX entry: (Update)
Hao Zheng. Specification and compilation of timed systems. Master's thesis, University of Utah, 1998. http://citeseer.ist.psu.edu/zheng98specification.html More
@misc{ zheng98specification,
author = "H. Zheng",
title = "Specification and compilation of timed systems",
text = "Hao Zheng. Specification and compilation of timed systems. Master's thesis,
University of Utah, 1998.",
year = "1998",
url = "citeseer.ist.psu.edu/zheng98specification.html" }
Citations (may not include all citations):139 An introduction to event structures (context) - Winskel - 1988
138 Synthesis of Self-Timed VLSI Circuits from Graph-theoretic S.. (context) - Chu - 1987 ACM
108 Programming in VLSI: from communicating processes to delay- .. (context) - Martin - 1990
105 Performance Analysis and Optimization of Asynchronous Circui.. - Burns - 1991 ACM DBLP
78 Synthesis of timed asynchronous circuits - Myers, Meng - 1993 ACM DBLP
53 Algorithms for interface timing verification (context) - McMillan, Dill - 1992 ACM DBLP
50 Automatic synthesis of asynchronous circuits from high-level.. (context) - Meng, Brodersen et al. - 1989
47 The Post Office experience: Designing a large asynchronous c.. - Davis, Coates et al. - 1993
47 The Post Office experience: Designing a large asynchronous c.. - Coates, Davis et al. - 1993
45 Computer-Aided Synthesis and Verification of Gate-Level Time.. - Myers - 1995 ACM
44 Synthesis of delayinsensitive modules (context) - Molnar, Fang et al. - 1985
38 Synthesis of Asynchronous Controllers for Heterogeneous Syst.. - Yun - 1994 ACM
29 Automatic Synthesis of Burst-Mode Asynchronous Controllers (context) - Nowick - 1993 ACM
27 Translating Concurrent Communicating Programs into Asynchron.. (context) - Brunvand - 1991 ACM
23 Automatic synthesis of gatelevel timed circuits with choice - Myers, Rokicki et al. - 1995
21 Specification and analysis of timing constraints in signal t.. (context) - Vanbekbergen, Goossens et al. - 1992
17 The VLSI-programming language Tangram and its translation in.. (context) - Berkel, Kessels et al. - 1991 ACM
16 Efficient timing analysis algorithms for timed state space e.. - Belluomini, Myers - 1997
15 Automatic verificaton of timed circuits (context) - Rokicki, Myers - 1994
10 Self-Timed Control of Concurrent Processes: The Design of Ap.. (context) - Varshavsky - 1990
7 considerations in the specification and synthesis of systems.. (context) - Subrahmanyam, in et al. - 1990
7 A family of normalized LMS algorithms - Douglas - 1994
6 Timed event/level structures - Belluomini, Myers
6 Automatic synthesis of gatelevel speed-independent circuits (context) - Beerel, Myers et al. - 1994
2 min calculation using a pruned ordered list (context) - max - 1996
2 A VLSI implementation of the MAXLIST algorithm (context) - Julsgaard, Xu - 1995
1 An asynchronous implementation of the maxlist algorithm - Myers, Zheng - 1997
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