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by Shiyou Zhao, Kaushik Roy, Cheng-kok Koh
In Proc. International Symposium on Physical Design
http://dynamo.ecn.purdue.edu/~chengkok/papers/ispd01_decap.ps
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Abstract:
We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. Decoupling capacitance budgets for the circuit modules are calculated based on the power supply noise estimates. A linear programming technique is used to maximize the allocation of the existing white space in the floorplan for the placement of decoupling capacitors. An incremental heuristic is proposed to insert more white space into the existing floorplan to meet the remaining demand required for decoupling capacitance fabrication. Experimental results on six MCNC benchmark circuits show that the white space allocated for decoupling capacitance is about 6 % 12 % of the chip area for the 0:25m technology, and the power supply noise can be kept below 10%Vdd.
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