Cached DRAM for ILP Processor Memory Access Latency Reduction (2001) [6 citations — 1 self]
Download:
by Zhichun Zhu, Xiaodong Zhang
IEEE Micro
http://www.cs.wm.edu/hpcs/WWW/HTML/publications/./papers/TR-01-6.pdf
Add To MetaCart
Abstract:
As the speed gap between processor and memory widens, data-intensive applications such as commercial workloads increase demands on main memory systems. Consequently, memory stall time—both latency time and bandwidth time—can increase dramatically, significantly impeding the performance of these applications. DRAM latency, or the minimum time for a DRAM to physically read or write data, mainly determines latency time. The data transfer rate through the memory bus determines bandwidth time. Burger, Goodman, and Kägi show that memory bandwidth is a major performance bottleneck in memory systems. 1 More recently, Cuppu et al. indicate that with improvements in bus technology, the most advanced memory systems, such as synchronous DRAM
Citations
| 1253 | The Simplescalar toolset, version 2.0 – Burger, Austin - 1997 |
| 158 | Memory bandwidth limitations of future microprocessors – Burger, Goodman, et al. - 1996 |
| 19 | A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality,” Proc. 33rd Int’l Symp. Microarchitecture – Zhang, Zhu, et al. - 2000 |
| 7 | Wcdram: A fully associative integrated cached-dram with wide cache lines – Koganti - 1997 |
| 7 | CDRAM in a Unified Memory Architecture – Hart - 1994 |
| 6 | Trends in semiconductor memories – Katayama - 1997 |
| 3 | Performance of Cached DRAM – Hsu, Smith - 1993 |
| 1 | Cuppu et al., “A Performance Comparison of Contemporary DRAM – unknown authors - 1999 |
| 1 | DRAM On-Chip Caching, tech. report – Wong, Baer - 1997 |
| 1 | et al., “The Cache DRAM Architecture: A DRAM with an On-Chip Cache Memory – Hidaka - 1990 |
