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by Lixin Zhang, Sally A. Mckee, Wilson C. Hsieh, John B. Carter
ftp://ftp2.cs.utah.edu/pub/users/sam/isca00ws.ps.gz
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Abstract:
Prefetching has long been used to mask the latency of memory loads. This paper presents results for an initial implementation of pointer-based prefetching within the Impulse adaptable memory controller. We conduct our experiments on a four-way issue superscalar machine. For the microbenchmarks we examine, we consistently realize about a 20 % improvement in execution time for linked data structures accessed within medium to short loop iterations. This compares favorably to software prefetching when the data working set fits in cache, and exceeds the performance of the latter technique for large working sets. We also find that a superscalar, outof-order processor hides the memory latency of linked data structures accessed in large loop iterations exceptionally well, which makes any pointer prefetching unnecessary.
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