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A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality (2000)  (Make Corrections)  (6 citations)
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
International Symposium on Microarchitecture



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Abstract: DRAM row-buffer conflicts occur when a sequence of requests on different rows goes to the same memory bank, causing much higher memory access latency than requests to the same row or to different banks. In this paper, we analyze the sources of row-buffer conflicts in the context of superscalar processors, and propose a permutation-based page interleaving scheme to reduce row-buffer conflicts and to exploit data access locality in the row-buffer. Compared with several existing schemes, we show... (Update)

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BibTeX entry:   (Update)

Z. Zhang, Z. Zhu, and X. Zhang. A permutation-based page interleaving scheme to reduce row-bu#er conflicts and exploit data locality. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-33), pages 32--41, Dec. 2000. http://citeseer.ist.psu.edu/zhang00permutationbased.html   More

@inproceedings{ zhang00permutationbased,
    author = "Zhao Zhang and Zhichun Zhu and Xiaodong Zhang",
    title = "A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality",
    booktitle = "International Symposium on Microarchitecture",
    pages = "32-41",
    year = "2000",
    url = "citeseer.ist.psu.edu/zhang00permutationbased.html" }
Citations (may not include all citations):
110   Memory bandwidth limitations of future microprocessors - Burger, Goodman et al. - 1996
107   Technical Report CS-TR (context) - Burger, Austin et al. - 1997
47   A performance comparison of contemporary DRAM architectures - Cuppu, Jacob et al. - 1999
38   Pseudo-randomly interleaved memory - Rau - 1991
33   Load latency tolerance in dynamically scheduled processors - Srinivasan, Lebeck - 1998
25   Memory access scheduling - Rixner, Dally et al. - 2000
22   Performance of cached DRAM organizations in vector supercomp.. (context) - Hsu, Smith - 1993
21   Design issues and tradeoffs for write buffers - Skadron, Clark - 1997
18   High-bandwidth interleaved memories for vector processors - .. (context) - Sohi - 1988
16   TPC Benchmark C Standard Specification (context) - Performance - 1998
14   Interleaved parallel schemes: Improving memory throughput on.. (context) - Seznec, Lenfant - 1992
12   The chinese remainder theorem and the prime memory system (context) - Gao - 1993
11   A characterization of processor performance in the VAX (context) - Emer, Clark - 1984
11   Performance evaluation of vector accesses in parallel memori.. (context) - Jump - 1986
8   SPEC CPU95 Version (context) - Evaluation - 1997
7   Analysis of vector access performance on skewed interleaved .. (context) - Chen, Liao - 1989
6   Conflict-free access of vectors with power-of-two strides (context) - Valero, Lang et al. - 1992
6   Low load latency through sum-addressed memory (context) - Lynch, Lauterbach et al. - 1998
6   The CYDRA 5 stride-insensitive memory system (context) - Rau, Schlansker et al. - 1989
4   Odd memory systems may be quite interesting (context) - Seznec, Lenfant - 1993
4   The design and verification of the AlphaStation 600 5-series.. (context) - Zurawski, Murray et al. - 1995
2   Mbit Direct RDRAM (context) - Inc - 2000
1   Technology for performance: Compaq professional workstation .. (context) - Corp - 1999
1   Technical Report UW CSE (context) - Wong, Baer et al. - 1997
1   Organizational design trade-offs at the DRAM (context) - Cuppu, Jacob - 1999
1   Scalable parallel memory architecture with a skew scheme (context) - Sakakibara, Kitai et al. - 1993
1   Keynote Address (context) - Wilkes, gap - 2000

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