Memory system support for dynamic cacheline assembly (2000) [4 citations — 1 self]
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by Lixin Zhang, Venkata K. Pingali, Bharat Ch, John B. Carter
In Proceedings of the Second Workshop on Intelligent Memory Systems
http://www2.cs.utah.edu/impulse/papers/ims00.ps.gz
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Abstract:
Processor clock rates are increasing 60 % per year, while DRAM latencies are decreasing only 7 % per year. Architects have developed many mechanisms, such as caching and prefetching, to bridge this performance gap, but none are particularly eective for irregular applications with poor spatial or temporal locality.
Citations
| 72 | RSIM reference manual, version 1.0 – Pai, Ranganathan, et al. - 1997 |
| 63 | Impulse: Building a smarter memory controller – Carter, Hsieh, et al. - 1999 |
| 48 | The fastest fourier transform in the west – Frigo, Johnson - 1997 |
| 15 | URSIM Reference Manual – Zhang |
