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Abstract: Introduction Since caches consume a significant fraction of total processor energy, e.g., 43% for StrongARM-1 [8], many studies have investigated energy-efficient cache designs [1, 5, 12, 13, 14, 15, 18]. However, none of these design studies have considered using content-addressable-memory (CAM) tags in highly-associative caches. This is particularly surprising given that the leading commercial lowpower processors over the last decade have all employed CAM-tag caches. For example, the ARM3... (Update)
Context of citations to this paper: More
.... the memory access patterns in our benchmarks and determine if we can make the speculative memory buffer 16 way or 32 way associative [22] without causing overflow in the memory buffer rows. In order to test our Superthreaded Architecture with coarse grained parallelism, we...
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BibTeX entry: (Update)
Michael Zhang and Krste Asanovic. Highlyassociative caches for low-power processors. Kool Chips Workshop, 33rd International Symposium on Microarchitecture, 2000. 12 http://citeseer.ist.psu.edu/zhang00highlyassociative.html More
@misc{ zhang00highlyassociative,
author = "M. Zhang and K. Asanovic",
title = "Highlyassociative caches for low-power processors",
text = "Michael Zhang and Krste Asanovic. Highlyassociative caches for low-power
processors. Kool Chips Workshop, 33rd International Symposium on Microarchitecture,
2000. 12",
year = "2000",
url = "citeseer.ist.psu.edu/zhang00highlyassociative.html" }
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82 The Filter Cache: An energy efficient memory structure - Kin, Gupta et al. - 1997
62 Cache design trade-offs for power and performance optimizati.. (context) - Su, Despain - 1995
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26 Power and performance tradeoffs using various cache configur.. - Albera, Bahar - 1998
20 Using dynamic cache management techniques to reduce energy i.. (context) - Bellas, Hajj et al. - 1999
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12 A replica technique for wordline and sense control in low-po.. - Amrutur, Horowitz - 1998
11 Energy optimization of multilevel cache architectures for RI.. (context) - Ko, Balsara et al. - 1998
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7 Speed and power scaling of SRAMs (context) - Amrutur, Horowitz - 2000
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1 quad-issue CMOS RISC microprocessor (context) - Benschneider, -MHz - 1995
1 Power saving feature Amulete (context) - Garside, saving et al. - 1998
The graph only includes citing articles where the year of publication is known.
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