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Abstract: State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for dispatching instructions to execution units based on dependencies, latencies, and resource availability. Most existing instruction schedulers are doing a less than optimal job of scheduling memory accesses and instructions dependent on them, for the following reasons: . Memory dependencies cannot be resolved prior to... (Update)
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BibTeX entry: (Update)
A. Yoaz, M. Erez, R. Ronen, and S. Jourdan, "Speculation Techniques for Improving Load Related Instruction Scheduling," in Proceedings of the 26 th Annual International Symposium on Computer Architecture, May 1999. http://citeseer.ist.psu.edu/yoaz99speculation.html More
@inproceedings{ yoaz99speculation,
author = "Adi Yoaz and Mattan Erez and Ronny Ronen and Stephan Jourdan",
title = "Speculation Techniques for Improving Load Related Instruction Scheduling",
booktitle = "{ISCA}",
pages = "42-53",
year = "1999",
url = "citeseer.ist.psu.edu/yoaz99speculation.html" }
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