Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun  Home/Search
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Abstract: A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a high performance microprocessor will typically send more accesses than the DRAM can handle due to the long cycle time of the embedded DRAM, especially in applications with significant memory requirements. A multi-bank DRAM can hide the long cycle time by allowing the DRAM to process multiple accesses in parallel, but... (Update)
Context of citations to this paper: More
...memory bank would carry with it an area overhead for additional circuits like Y decoders, read write datapath, etc. Yamauchi et.al. [144] estimate 40 and 80 overhead for 16 and 32 banks respectively, compared to a baseline 4 bank 256Mbit DRAM design. To take advantage of...
...when those references are satisfied in order. Several memory access schedulers have been proposed as part of systems on a chip [WAM 99] [YHO97]. Hitachi has built a test chip of their access optimizer for embedded DRAM that contains the access optimizer and DRAM [WAM 99] A...
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BibTeX entry: (Update)
T. Yamauchi, L. Hammond, and K. Olukotun. "The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors". In Advanced Research in VLSI, Ann Arbor, MI, USA, 15-16 September 1997. pp. 303--319. http://citeseer.ist.psu.edu/yamauchi97hierarchical.html More
@misc{ yamauchi97hierarchical,
author = "T. Yamauchi and L. Hammond and K. Olukotun",
title = "The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory
Integrated with Processors",
text = "T. Yamauchi, L. Hammond, and K. Olukotun. The Hierarchical Multi-Bank DRAM:
A High-Performance Architecture for Memory Integrated with Processors. In
Advanced Research in VLSI, Ann Arbor, MI, USA, 15-16 September 1997. pp.
303--319.",
year = "1997",
url = "citeseer.ist.psu.edu/yamauchi97hierarchical.html" }
Citations (may not include all citations):97 The Case for a Single-Chip Multiprocessor (context) - Olukotun, Nayfeh et al. - 1996
75 The MIPS R10000 Superscalar Microprocessor (context) - Yeager - 1996
64 Missing the Memory Wall: The Case for Processor/Memory Integ.. (context) - Saulsbury, Pong et al. - 1996
38 Evaluation of Design Alternatives for a Multiprocessor Micro.. (context) - Nayfeh, Hammond et al. - 1996
12 The SUIF Compiler System:A Parallelizing and Optimizing Rese.. (context) - Wilson, French et al. - 1994
9 The SimOS approach (context) - Rosenblum, Herrod et al. - 1995
9 A Single-Chip Multiprocessor Integrated with DRAM - Yamauchi, Hammond et al. - 1997
2 Skew Minimization Techniques for 256Mbit Synchronous DRAM an.. (context) - Han, Lee et al. - 1996
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