Chun Xia, Josep Torrellas  Home/Search
Context Related
Links: ACM | uiuc.edu/pub/researchgr...comprehen.ps uiuc.edu/iacomapapers/comprehen.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: uiuc.edu/iacoma/papers (more) From: uiuc.edu/papers (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: High-performance multiprocessor workstations are becoming increasingly popular. Since many of the workloads running on these machines are operating-system intensive, we are interested in what sort of support for the operating system should the memory hierarchy of these machines provide. This paper addresses this question. This paper shows that the largest performance losses for the operating system in a sophisticated 3-level cache hierarchy are due to off-chip cache misses, write buffer... (Update)
Context of citations to this paper: More
.... operating system, where processors read linked lists and often use complex data structures with indirection have low spatial locality [18]. Figure 7 shows the memory stall time expressed as memory stall time per instruction (MCPI) The stall time is shown separately for the...
.... Error and bound checking related branches are abundant in operating system because it has to be designed to handle all possible situations [22]. Table 2. Branch frequency and mix (jit: JIT compilation, intr: interpretation) Kernel User Branches per Instruction Branches per...
Cited by: More
Run-time Modeling and Estimation of Operating System Power.. - Li, John (2003) (Correct)
Branch Behavior of Java Runtime Systems and its.. - Li, John.. (2000) (Correct)
Understanding Control Flow Transfer and its Predictability in.. - Li, John (2001) (Correct)
Similar documents (at the sentence level):
9.5%: Instruction Prefetching of Systems Codes With Layout Optimized.. - Chun Xia (1996) (Correct)
7.7%: Exploiting Multiprocessor Memory Hierarchies For Operating Systems - Xia (1996) (Correct)
Active bibliography (related documents): More All
0.2: Performance Issues for Multiprocessor Operating Systems - Gamsa, Krieger, Parsons.. (1995) (Correct)
0.2: An Analysis of Operating System Behavior on a.. - Redstone, Eggers, Levy (2000) (Correct)
0.2: An Analysis of Software Interface Issues for SMT Processors - Redstone (2002) (Correct)
Similar documents based on text: More All
0.1: Improving the Data Cache Performance of Multiprocessor Operating .. - Chun Xia (1996) (Correct)
0.1: Optimizing the Instruction Cache Performance of the.. - Torrellas, Xia, Daigle (1995) (Correct)
0.1: Software Trace Cache - Ramírez, Larriba-Pey.. (1999) (Correct)
Related documents from co-citation: More All
4: Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary.. (context) - Hsieh, Gyllenhall et al. - 1996
3: Performance Factors for Superscalar Processors - Bennett, Flynn - 1995
3: Complete Computer System Simulation: The SimOS Approach - Rosenblum, Herrod et al. - 1995
BibTeX entry: (Update)
C. Xia and J. Torrellas, Comprehensive Hardware and Software Support for Operating Systems to Exploit MP Memory Hierarchies, IEEE Transactions on Computers, vol. 48, no. 5, pages 494-505, May, 1999. http://citeseer.ist.psu.edu/xia99comprehensive.html More
@article{ xia99comprehensive,
author = "Chun Xia and Josep Torrellas",
title = "Comprehensive Hardware and Software Support for Operating Systems to Exploit",
journal = "IEEE Transactions on Computers",
volume = "48",
number = "5",
pages = "494-505",
year = "1999",
url = "citeseer.ist.psu.edu/xia99comprehensive.html" }
Citations (may not include all citations):443 Improving Direct-Mapped Cache Performance by the Addition of.. - Jouppi - 1990 ACM DBLP
217 The Perfect Club Benchmarks: Effective Performance Evaluatio.. - Berry - 1989
176 Why Aren't Operating Systems Getting Faster as Fast as Hardw.. - Ousterhout - 1990
155 Cache Coherence Protocols: Evaluation Using a Multiprocessor.. (context) - Archibald, Baer - 1986 ACM DBLP
118 The Interaction of Architecture and Operating System Design - Anderson, Levy et al. - 1991 ACM DBLP
110 The Impact of Operating System Structure on Memory System Pe.. - Chen, Bershad - 1993 ACM DBLP
107 Achieving High Instruction Cache Performance with an Optimiz.. (context) - Hwu, Chang - 1989 ACM DBLP
91 The Impact of Architectural Trends on Operating System Perfo.. (context) - Rosenblum, Bugnion et al. - 1995 ACM DBLP
86 Cache Performance of Operating System and Multiprogramming W.. (context) - Agarwal, Hennessy et al. - 1988 ACM DBLP
67 Contrasting Characteristics and Cache Performance of Technic.. (context) - Maynard, Donnelly et al. - 1994 ACM DBLP
52 Instruction Fetching: Coping with Code Bloat (context) - Uhlig, Nagle et al. - 1995 DBLP
51 Optimizing Instruction Cache Performance for Operating Syste.. - Torrellas, Xia et al. - 1995 ACM DBLP
36 Characterizing the Caching and Synchronization Performance o.. (context) - Torrellas, Gupta et al. - 1992 ACM DBLP
16 Memory System Performance of UNIX on CC-NUMA Multiprocessors (context) - Chapin, Herrod et al. - 1995 ACM DBLP
11 Instruction Prefetching of Systems Codes With Layout Optimiz.. - Xia, Torrellas - 1996
6 Improving the Data Cache Performance of Multiprocesor Operat.. - Xia, Torrellas - 1996
Documents on the same site (http://polaris.cs.uiuc.edu/iacoma/papers.html): More
Optimizing Instruction Cache Performance for Operating.. - Torrellas, Xia, Daigle (1995) (Correct)
False Sharing and Spatial Locality in Multiprocessor Caches - Torrellas, Lam, Hennessy (1992) (Correct)
The Impact of Speeding up Critical Sections with Data.. - Trancoso, Torrellas (1996) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC