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Abstract: Integrating 1 support for block data transfer has become an im- portant emphasis in recent cache-coherent shared address space multiprocessors. This paper examines the potential performance benefits of adding this support. A set of ambitious hardware mechanisms is used to study performance gains in five important scientific computations that appear to be good candidates for using block transfer. Our conclusion is that the benefits of block transfer are not substantial for hardware cache-... (Update)
Context of citations to this paper: More
...and an upper triangular matrix. The factorization uses blocking to exploit temporal locality w.r.t. individual submatrix elements [12]. Originally designed to run on shared memory systems, this benchmark can only be used on a single SMP node of the IBM SP. Some...
.... N body method) FFT (complex 1 D version of the radix # # six step FFT algorithm [Bai90] LU (blocked LU decomposition, see [WSH94] for more details) CLU (blocked LU decomposition with contiguous allocation of data, more optimized version of LU) Radix (integer radix...
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BibTeX entry: (Update)
S.C. Woo, J.P. Singh, and J.L. Hennessy. The performance advantages of integrating block data transfer in cache-coherent multiprocessors. In Proceedings of the 6th Symposium on Architectural Support for Programming Languages and Operating Systems, pages 219--231, October 1994. http://citeseer.ist.psu.edu/woo94performance.html More
@inproceedings{ woo94performance,
author = "Steven Cameron Woo and Jaswinder Pal Singh and John L. Hennessy",
title = "The Performance Advantages of Integrating Block Data Transfer in Cache-Coherent Multiprocessors",
booktitle = "{\em Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems}",
address = "San Jose, California",
pages = "219--229",
year = "1994",
url = "citeseer.ist.psu.edu/woo94performance.html" }
Citations (may not include all citations):362 The Stanford FLASH Multiprocessor (context) - Kuskin - 1994 ACM DBLP
357 The Directory-Based Cache Coherence Protocol for the DASH Mu.. (context) - Lenoski, Laudon et al. - 1990
301 The Midway Distributed Shared Memory System (context) - Bershad, Zekauskas et al. - 1993 ACM
268 Tempest and Typhoon: User-level Shared Memory - Reinhardt, Lares et al. - 1994 DBLP
267 Multi-Level Adaptive Solutions to Boundary-Value Problems (context) - Brandt - 1977
212 APRIL: A Processor Architecture for Mul- tiprocessing - Agarwal, Lim et al. - 1990
182 A Comparison of Sorting Algorithms for the Connection Machin.. - Blelloch - 1991
138 SPLASH: Stanford Parallel Applications for Shared Memory (context) - Singh, Weber et al. - 1992
96 Integrating Message-Passing and Shared-Memory: Early Experie.. - Kranz - 1993 ACM DBLP
61 FFTs in External or Hierarchical Memory - Bailey - 1990 ACM DBLP
45 Simulation of Multiprocessors: Accuracy and Performance (context) - Goldschmidt - 1993
15 Scaling Parallel Programs for Multiprocessors: Methodology a.. (context) - Singh, Hennessy et al. - 1993
8 An Evaluation of Software Distributed Shared Memory for Next.. (context) - Dwarkadas, Keleher et al. - 1993
8 The Performance Advantages of Integrating Message Passing in.. (context) - Woo, Singh et al. - 1993 ACM
5 The NAS Parallel Benchmarks - Bailey - 1991
2 Cray TD System Architecture and Overview (context) - Inc, Architecture et al. - 1993
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