| Alternate document: Details Design Tradeoffs for Embedded Network Processors (02) Tilman Wolf, Mark A. Franklin |
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Abstract: The flexibility to adapt to new services and protocols without changes in the underlying hardware is and will increasingly be a key requirement for advanced networks. Introducing a processing component into the data path of routers and implementing packet processing in software provides this ability. In such a programmable router, a powerful processing infrastructure is necessary to achieve a level of performance that is comparable to custom silicon-based routers and to demonstrate the... (Update)
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BibTeX entry: (Update)
T. Wolf. Design and Performance of a Scalable HighPerformance Programmable Router. PhD thesis, Department of Computer Science, Washington University in St. Louis, May 2002. http://citeseer.ist.psu.edu/wolf02design.html More
@inproceedings{ wolf02design,
author = "Tilman Wolf and Mark A. Franklin",
title = "Design Tradeoffs for Embedded Network Processors",
booktitle = "{ARCS}",
pages = "149--164",
year = "2002",
url = "citeseer.ist.psu.edu/wolf02design.html" }
Citations (may not include all citations):
485
The JPEG still picture compression standard (context) - Wallace - 1991
458
A universal algorithm for sequential data compression
- Ziv, Lempel
367
Computer Architecture -- A Quantitative Approach (context) - Hennessy, Patterson - 1995
320
MediaBench: A tool for evaluating and synthesizing multimedi..
- Lee, Potkonjak et al. - 1997
299
The BSD packet filter: A new architecture for user-level pac..
- McCanne - 1993
292
Service disciplines for guaranteed performance service in pa..
- Zhang - 1995
275
Shade: A fast instruction-set simulator for execution profil..
- Cmelik, Keppel - 1994
251
Simultaneous multithreading: Maximizing on-chip parallelism
- Tullsen, Eggers et al. - 1995
237
The design philosophy of the DARPA internet protocols
- Clark - 1988
170
The National Technology Roadmap for Semiconductors (context) - Association - 2001
121
Start-time fair queuing: A scheduling algorithm for integrat..
- Goyal, Vin et al. - 1996
101
IEEE Transactions on Parallel and Distributed Systems (context) - Agarwal, multithreaded - 1992
97
The RC5 encryption algorithm
- Rivest - 1995
83
Smart Packets for active networks
- Schwartz, Jackson et al. - 1999
67
An elementary processor architecture with simultaneous instr.. (context) - Hirata, Kimura et al. - 1992
65
Dhrystone: A synthetic systems programming benchmark (context) - Weicker - 1984
62
A generalized processor sharing approach to flow control: Th.. (context) - Parekh, Gallager - 1992
61
The IP network address translator (context) - Egevang, Francis - 1994
58
A self clocked fair queuing scheme for broadband application.. (context) - Golestani - 1994
58
Design of a gigabit ATM switch
- Chaney, Fingerhut et al. - 1997
57
Error-Control Coding for Computer Systems (context) - Rao, Fujiwara - 1989
55
Cramming more components onto integrated circuits (context) - Moore - 1965
51
Darwin: Customizable resource management for value-added net..
- Chandra, Chu et al. - 2001
48
A survey of active network research
- Tennenhouse, Smith et al. - 1997
44
the design and security of block ciphers (context) - Lai - 1992
44
CommBench - a telecommunications benchmark for network proce..
- Wolf, Franklin - 2000
43
Practical programmable packets
- Moore, Hicks et al. - 2001
42
An active router architecture for multicast video ditributio..
- Keller, Choi et al. - 2000
35
NodeOS interface specification (context) - Peterson - 2001
34
Imagine: Media processing with streams (context) - Khailany, Dally et al. - 2001
33
Reduced instruction set computers (context) - Patterson - 1985
31
Thread scheduling for cache locality
- Philbin, Edler et al. - 1996
31
NetBench: A benchmarking suite for network processors
- Memik, Mangione-Smith et al. - 2001
30
Towards an active network architecture
- Tennenhouse, Wetherall - 1996
30
Computer Communication Review (context) - Campbell, De Meer et al. - 1999
30
Worst case fair weighted fair queuing (context) - Bennett, Zhang - 1995
30
Characterizing processor architectures for programmable netw..
- Crowley, Fiuczynski et al. - 2000
29
Bowman: A node OS for active networks
- Merugu, Bhattacharjee et al. - 2000
29
Simple and flexible datagram access controls for UNIX-based ..
- rey, Mogul - 1989
29
Rate proportional servers: A design methodology for fair que..
- Stiliadis, Varma - 1998
29
Configuring sessions in programmable networks
- Choi, Turner et al. - 2001
22
Scheduling computations on a software-based router (context) - Qie, Bavier et al. - 2001
21
Active networks: Applications (context) - Psounis - 1999
21
Design issues for high performance active routers
- Wolf, Turner - 2001
21
Design issues for high performance active routers
- Wolf, Turner - 2000
20
high performance active network node (context) - Decasper, Parulkar et al. - 1999
19
IEEEACM Transaction Networking (context) - Floyd, early et al. - 1993
18
Router Plugins - a modular and extensible software framework..
- Decasper, Dittia et al. - 1998
18
The CAST-128 encryption algorithm
- Adams - 1997
18
Intel IXP1200 Network Processor (context) - Corp - 2000
17
Dinero IV Trace-Driven Uniprocessor Cache Simulator (context) - Edler, Hill - 1998
16
Concast: Design and implementation of an active network serv.. (context) - Calvert, Gri et al. - 2001
16
Design space exploration of network processor architectures
- Thiele, Chakraborty et al. - 2002
15
fly programmable hardware for networks
- Hadzic, Marcus et al. - 1998
15
Beyond Moore's law: Internet growth trends (context) - Roberts - 2000
15
Understanding network processors (context) - Shah - 2001
15
TPC Benchmark C (context) - Performance - 1998
14
A network processor performance and design model with benchm..
- Franklin, Wolf - 2002
14
Bowman and canes: Implementation of 143 an active network
- Merugu, Bhattacharjee et al. - 1999
13
IEEE Network Special Issue on Active and Controllable Networ.. (context) - Alexander, Arbaugh et al. - 1998
12
A hierarchial cpu scheduler for multimedia operating systems (context) - Goyal, Vin et al. - 1996
11
Fair queuing for aggregated multiple links
- Blanquer, Ozden - 2001
11
Technical Reference Manual (context) - Ltd, E-S - 1999
11
Sun Microsystems Laboratories (context) - Cmelik, user's et al. - 1993
11
Strong security for active networks
- Murphy, Lewis et al. - 2001
11
The smart port card: An embedded UNIX processor architecure .. (context) - DeHart, Richard et al. - 2001
9
Expressing meaningful processing requirements among heteroge..
- Galtier, Mills et al. - 2000
8
Workloads for programmable network interfaces
- Crowley, Fiuczynski et al. - 1999
8
Scheduling processing resources in programmable routers
- Pappu, Wolf - 2002
8
SPEC CPU95 - Version (context) - Evaluation - 1995
6
Benchmarking network processors (context) - Chandra, Yavatkar et al. - 2002
5
cient fair queuing using deficit round robin (context) - Shreedhar, Varghese - 1995
5
Aggregated hierarchical multicast for active networks
- Wolf, Choi - 2001
5
Department of Computer Science (context) - Burger, Austin et al. - 1997
5
JADE - Embedded MIPS Processor Core (context) - Technologies - 1998
4
IBM Power Network Processors (context) - Corp - 2000
4
Hierarchial packet fair queuing algorithms (context) - Bennett, Zhang - 1996
4
TS704 Edge Processor Product Brief (context) - sqware - 1999
4
Digital Communications Processor (context) - Corporation - 1999
4
Design of a high performance dynamically extensible router
- Kuhns, DeHart et al. - 2002
4
Locality-aware predictive scheduling for network processors
- Wolf, Franklin - 2001
3
Network Processor Family (context) - Inc - 2000
3
comproductpowerpccorecr wp (context) - Microelectronics, PowerPC et al. - 1998
3
Microprocessors circa (context) - Gelsinger, Gargini et al. - 1989
3
NetVortex Network Communications System Multiprocessor NPU (context) - Inc - 2000
3
A processor architecture for multiprocessing (context) - Agarwal, Lim et al. - 1990
3
A modelling framework for network processor systems (context) - Crowley, Baer - 2002
2
nity on processor scheduling for multiprogrammed (context) - Vaswani, Zahorjan et al. - 1991
2
Series Gigabit Switch Routers (context) - Systems, Cisco - 1999
2
Packet classification using tuple space search (context) - Srinivasan, Suri et al. - 1999
2
Using processor cache a#nity information in shared-memory mu.. (context) - Squillante, Lazowska - 1993
2
Issues in implementation of cache-a#nity scheduling (context) - Devarakonda, Mukherjee - 1992
2
Design of a weighted fair queueing cell scheduler for ATM ne.. (context) - Chen, Turner - 1998
2
for embedded network processors (context) - Wolf, Franklin - 2002
2
PayloadPlus Fast Pattern Processor (context) - Inc - 2000
1
WaveVideo -- an integrated approach to adaptive wireless vid.. (context) - Frankhauser, Dasen et al. - 1999
1
implementation and performance of a content-based switch (context) - Apostolopoulos, Aubespin et al. - 2000
1
Active pipes: Program composition for programmable networks (context) - Keller, Ramamirtham et al. - 2001
1
High-capacity lightwave transmission experiments (context) - Chraplyvy - 1999
1
Fabrice Tchakountio (context) - Snoeren, Partridge et al. - 2001
1
Fast scalable algorithms for level four switching (context) - Srinivasan, Varghese et al. - 1998
1
Curnow and Brian (context) - Harold - 1976
1
A methodology and simulator for the study of network process.. (context) - Suryanarayanan, Byrd et al. - 2002
1
Evaluating the performance of cache-a#nity scheduling in sha.. (context) - Torrellas, Tucker et al. - 1995
1
nity-based scheduling in multiprocessor networking (context) - Salehi, Kurose et al. - 1996
1
Clock rate versus IPS: The end of the road for conventional .. (context) - Agarwal, Hrishikesh et al. - 2000
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