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Abstract: ix 1 (Update)
Context of citations to this paper: More
.... bu ers, dynamic branch predictions and dynamic speculative executions [HP96] Data cache analysis has been proposed in [WMH 97, Whi97] 6 . The results can typically be formulated as every i :th execution of an instruction will generate a data cache miss . As an...
.... output state(B) data lines(D could conflict with) Figure 3: Algorithm to Calculate Data Cache States from fully optimized code see [16]. 3.2. Calculation of Virtual Addresses Calculating addresses that are relative to the beginning of a global variable or an activation...
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Timing Analysis for Data and Wrap-Around Fill Caches - White, Mueller, al. (1999) (Correct)
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BibTeX entry: (Update)
R. White, D. B. Whalley, and M. G. Harmon. Bounding worst-case data cache performance. In IEEE Real-Time Systems Symposium, December 1996. (submitted). http://citeseer.ist.psu.edu/white96bounding.html More
@misc{ white96bounding,
author = "R. White and D. Whalley and M. Harmon",
title = "Bounding worst-case data cache performance",
text = "R. White, D. B. Whalley, and M. G. Harmon. Bounding worst-case data cache
performance. In IEEE Real-Time Systems Symposium, December 1996. (submitted).",
year = "1996",
url = "citeseer.ist.psu.edu/white96bounding.html" }
Citations (may not include all citations):1399 Compilers -- Principles (context) - Aho, Sethi et al. - 1986
474 A data locality optimizing algorithm (context) - Wolf, Lam - 1991
344 Design and evaluation of a compiler algorithm for prefetchin.. - Mowry, Lam et al. - 1992
167 Calculating the maximum execution time of real-time programs (context) - Puschner, Koza - 1989
91 An accurate worst case timing analysis for risc processors - Lim, Bea et al. - 1994
85 Predicting program execution times by analyzing static and d.. (context) - Park - 1993
83 Bounding worstcase instruction cache performance (context) - Arnold, Mueller et al. - 1994
83 A retargetable technique for predicting execution time - Harmon, Baker et al. - 1992
81 The SPARC Architecture Manual - Inc - 1992
79 A portable global optimizer and linker (context) - Benitez, Davidson - 1988
61 Integrating the timing analysis of pipelining and instructio.. (context) - Healy, Whalley et al. - 1995
55 Pipelined processors and worst case execution times - Zhang, Burns et al.
49 Cache modeling for real-time software: Beyond direct mapped .. (context) - Li, Malik et al. - 1996
46 Efficient microarchitecture modeling and path analysis for r.. - Li, Malik et al. - 1995
40 Timing analysis for data caches and set-associative caches - White, Mueller et al. - 1997
31 Efficient worst-case timing analysis of data caching - Kim, Min et al. - 1996
24 Static Cache Simulation and its Applications - Mueller - 1994
21 A design environment for addressing architecture and compile.. - Davidson, Whalley - 1991
13 Quick compilers using peephole optimizations - Davidson, Whalley - 1989
11 Generalizing timing predictions to set-associative caches - Mueller - 1997
8 Static analysis of cache analysis for real-time programming (context) - Rawat - 1995
5 Worst case timing analysi risc processor RR case study - Lim, Park et al. - 1995
5 Bounding instruction cache performance (context) - Arnold - 1996
5 Supporting the specification and analysis of timing constrai.. (context) - Ko, Healy et al. - 1996
4 TMSS Integrated SPARC Processor (context) - TMS, Processor - 1993
3 Worst-case timing analysis of instruction caches with wrap-a.. (context) - Healy, Whalley et al. - 1996
3 Supporting user-friendly analysis of timing constraints (context) - Ko, Whalley et al. - 1995
1 Predicting pipeline and instruction cache performance (context) - Healy - 1995
The graph only includes citing articles where the year of publication is known.
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