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Abstract: This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique is Caching Address Tags, or CAT cache, for short. The CAT cache exploits locality property that exists among addresses of memory references. By keeping only a limited number of distinct tags of cached data, rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude... (Update)
Context of citations to this paper: More
.... address bus [18] Works closer to the scope of this paper propose an organization that reduces the area cost of address tags in caches [23][25]. These organizations are similar to TLAS but our proposal has a simpler control logic. It does not need to maintain the exact...
.... consumption [34] Much effort has been devoted to allocating minimal cache structures and optimizing code for effective cache utilization [57]. A particularly successful technique is cache line coloring [29] Given a code segment and input data benchmarks, cache linecoloring...
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4: Decoupled sectored caches: reconciliating low tag volume and low miss ratio (context) - Seznec - 1994
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BibTeX entry: (Update)
H. Wang, T. Sun, Q. Yang, "Minimizing Area Cost of on-Chip Cache Memories by Caching Address Tags", IEEE Transactions on Computers, 46(11) (1997), pp. 1187-1201. http://citeseer.ist.psu.edu/wang97minimizing.html More
@article{ wang97minimizing,
author = "Hong Wang and Tong Sun and Qing Yang",
title = "Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags",
journal = "IEEE Transactions on Computers",
volume = "46",
number = "11",
pages = "1187-1201",
year = "1997",
url = "citeseer.ist.psu.edu/wang97minimizing.html" }
Citations (may not include all citations):200 Principles of CMOS VLSI Design (context) - Weste, Eshraghian - 1985
111 Using Cache Memory to Reduce Processor-Memory Traffic (context) - Goodman - 1983
103 A Case for Direct-Mapped Caches (context) - Hill - 1988
85 Cache Write Policies and Performance - Jouppi - 1993
78 Data Prefetching in Multiprocessor Vector Cache Memories (context) - Fu, Patel - 1991
71 An Area Model for On-Chip Memories and Its Application (context) - Mulder, Quach et al. - 1991
65 Computer Technology and Architecture: An Evolving Interactio.. (context) - Hennessy, Jouppi - 1991
61 The Effect of Sharing on the Cache and Bus Performance of Pa.. (context) - Eggers, Katz - 1989
51 Texas Instruments - Cache, Data - 1992
49 False Sharing and Spatial Locality in Multiprocessor Caches - Torrelas, Lam et al. - 1994
46 Tracing with Pixie (context) - Smith - 1991
37 Alpha AXP Architecture (context) - Sites - 1992
24 Cache Performance of the SPEC92 Benchmark Suite (context) - Gee, Hill et al. - 1993
19 Optimal Allocation of On-Chip Memory for Multiple-API Operat.. (context) - Nagle, Uhlig et al. - 1994
17 Dynamic Base Register Caching: A Technique for Reducing Addr.. - Farrens, Park - 1991
15 A Study of Single-Chip Processor/Cache Organizations for Lar.. - Farrens, Tyson et al. - 1994
15 Decoupled Sectored Caches: Conciliating Low Tag Implementati.. - Seznec - 1994
14 Analysis and Comparison of Cache Coherence Protocols for a P.. (context) - Yang, Bhuyan et al. - 1989
11 Information Content of CPU Memory Referencing Behavior (context) - Hammerstrom, Davidson - 1977
8 Introducing a New Cache Design into Vector Computers (context) - Yang - 1994
3 Adjustable Block Size Coherence Caches (context) - Dubnicki, LeBlanc - 1992
2 Memory Hierarchies for Directly Executed Language Microproce.. (context) - Alpert - 1984
2 An Address Prediction Mechanism for Reducing Processor-Memor.. (context) - Pleszkun, Rau et al. - 1981
1 A One's Complement Cache (context) - Yang, Adina - 1994
1 A 200-MFLOPS 100-MHz 64-b BiCMOS Vector -Pipelined Processor.. (context) - Okamoto - 1991
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