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Abstract: Growing interest in ambitious multiple-issue machines and heavilypipelined machines requires a careful examination of how much instructionlevel parallelism exists in typical programs. Such an examination is complicated by the wide variety of hardware and software techniques for increasing the parallelism that can be exploited, including branch prediction, register renaming, and alias analysis. By performing simulations based on instruction traces, we can model techniques at the limits of... (Update)
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BibTeX entry: (Update)
David W. Wall, Limits of Instruction Level Parallelism, Proc. 4th ASPLOS, http://citeseer.ist.psu.edu/wall90limits.html More
@inproceedings{ wall91limits,
author = "D. W. Wall",
title = "Limits of Instruction-Level Parallelism",
booktitle = "Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating System ({ASPLOS})",
journal = "SIGPLAN Notices",
volume = "26",
number = "4",
publisher = "ACM Press",
address = "New York, NY",
isbn = "0-89791-380-9",
pages = "176--189",
year = "1991",
url = "citeseer.ist.psu.edu/wall90limits.html" }
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252 Analysis of pointers and structures (context) - Chase, Wegman et al. - 1990 ACM DBLP
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38 Parallel processing: A smart compiler and a dumb machine (context) - Fisher, Ellis et al. - 1984 DBLP
12 Detection and parallel execution of parallel instructions (context) - Tjaden, Flynn - 1970
3 High performance reduced instruction set processors (context) - Agarwala, Cocke - 1987
3 Eighth Annual Symposium on Computer Architecture (context) - Smith, of et al. - 1986
2 Stanford benchmark suite (context) - Hennessy
1 Thirteenth Annual Symposium on Computer Architecture (context) - McFarling, Hennessy et al. - 1986
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