(Enter summary)
Abstract: Now that the field of automated synthesis for register transfer
level integrated circuit design is beginning to mature, it is appropriate to
begin developing tools for higher levels of design. At the next higher level, it
is appropriate to explore behavioral and structural partitioning, answering
such questions about the design as:
. Should the design be implemented on a single VLSI chip, or
partitioned into two or more chips, and if it is to be partitioned, where
should the behavior be... (Update)
Context of citations to this paper: More
.... applied optimizations such as algebraic transformations, re timing and code motions across multiplexors for improved synthesis results [13, 14]. More recent work during the last decade has presented speculative code motions for mixed control data flow type of designs...
.... applied optimizations such as algebraic transformations, re timing and code motions across multiplexors for improved synthesis results [11, 12]. Subsequent work has presented speculative code motions for mixed control data flow type of designs and demonstrated their effects on...
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System Specification and Storage Architecture Exploration for.. - Moolenaar (1996)
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0.4: Synthesis of Asynchronous Systems from Data Flow Specifications - Wuu, Vrudhula (1993)
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15: Optimizing the Resource Utilization Using Transformations (context) - Potkonjak, Rabaey - 1991
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BibTeX entry: (Update)
R. Walker and D. Thomas, "Behavioral transformation for algorithmic level IC design," IEEE Transactions on Computer-Aided Design, October 1989. http://citeseer.ist.psu.edu/walker89behavioral.html More
@article{ walker89behavioral,
author = "R. Walker and D. Thomas",
title = "Behavioral transformation for algorithmic level {IC} design",
journal = "{IEEE} Trans. on CAD",
year = "1989",
url = "citeseer.ist.psu.edu/walker89behavioral.html" }
Citations (may not include all citations):
53
Sehwa: A Software Package for Synthesis of Pipelines from Be.. (context) - Park, Parker - 1988
41
Parallel and Pipelined VLSI Implementation of Signal Process.. (context) - Dewilde, Deprettere et al. - 1985
40
Tutorial on High Level Synthesis (context) - McFarland, Parker et al. - 1988
27
Partitioning Before Logic Synthesis (context) - Camposano, Brayton - 1987
26
Flamel: A High-Level Hardware Compiler (context) - Trickey - 1987
20
The System Architect's Workbench
- Thomas, Dirkes et al. - 1988
19
Force-Directed Scheduling in Automatic Data Path Synthesis (context) - Paulin, Knight - 1987 ACM DBLP
16
Behavioral Synthesis with Interfaces (context) - Nestor, Thomas - 1986
13
Instruction Set Processor Specifications (context) - Barbacci - 1981
8
Methods of Automatic Data Path Synthesis (context) - Thomas, Hitchcock et al. - 1983
7
High Level Synthesis: Current Status and Future Directions (context) - Borriello, Detjens - 1988
5
Design Representation and Transformation in The System Archi.. (context) - Walker, Thomas - 1987
5
Automation of Module Set Independent RegisterTransfer Level .. (context) - Snow - 1978
3
A Model of Design Representation and Synthesis (context) - Walker, Thomas - 1985 ACM
1
Behavioral Level Transformation in the CMU-DA System (context) - Walker, Thomas - 1983 ACM
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://intrepid.mcs.kent.edu/~walker/papers/index.html): More
Efficiently Searching the Optimal Design Space - Blythe, Walker (1999)
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Toward a Practical Methodology for Completely Characterizing.. - Blythe, Walker (1996)
(Correct)
Computing Lower Bounds on Functional Units Before Scheduling - Chaudhuri, Walker (1994)
(Correct)
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