K. N. Vikram and V. Vasudevan  Home/Search
Context Related
| googlepages.com/MPMS05.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: googlepages.com/publications (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: One of the most flexible and modular approaches to reconfigurable systems is a bus-based approach. In order to get realistic performance estimates of these systems, detailed modeling of the processor as well as the bus and memory hierarchy is required. In addition, when coupling one or more reconfigurable units with a superscalar, out-of-order issue, load/store RISC CPU using the on-chip system bus, there are issues relating to cache coherency that need to be addressed. We have developed a... (Update)
Cited by: More
Mapping Data-Parallel Tasks Onto Partially Reconfigurable.. - Vikram, Vasudevan (2006) (Correct)
Active bibliography (related documents): More All
0.5: Virtualizing Hardware with Multi-Context Reconfigurable.. - Enzler, Plessl, Platzner (Correct)
0.5: A Survey of HW/SW Cosimulation Techniques and Tools - Hubert (1998) (Correct)
0.5: Sesame: Simulation of Embedded System.. - van Halderen.. (2001) (Correct)
Similar documents based on text:
5.0: Unknown - (Correct)
BibTeX entry: (Update)
K. N. Vikram and V. Vasudevan, "Hardware-software co-simulation of bus-based reconfigurable systems," Microprocess. Microsyst., vol. 29, no. 4, pp. 133--144, May 2005. http://citeseer.ist.psu.edu/vikram05hardwaresoftware.html More
@misc{ vikram05hardwaresoftware,
author = "K. Vikram and V. Vasudevan",
title = "Hardware-software co-simulation of bus-based reconfigurable systems",
text = "K. N. Vikram and V. Vasudevan, Hardware-software co-simulation of bus-based
reconfigurable systems, Microprocess. Microsyst., vol. 29, no. 4, pp. 133--144,
May 2005.",
year = "2005",
url = "citeseer.ist.psu.edu/vikram05hardwaresoftware.html" }
Citations (may not include all citations):1575 Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1990
458 A Universal Algorithm for Sequential Data Compression - Ziv, Lempel - 1977
373 Unix Network Programming (context) - Stevens - 1990
176 Garp: A MIPS Processor with a Reconfigurable Coprocessor - Hauser, Wawrzynek - 1997
67 The SimpleScalar Toolset Version - Burger, Austin - 1997
65 The Chimaera Reconfigurable Functional Unit - Hauck, Fry et al. - 1997
63 Piperench: A Coprocessor for Streaming Multimedia Accelerati.. - Goldstein, Schmit et al. - 1999
59 DPGA-Coupled Microprocessors: Commodity ICs for the Early 21.. - DeHon - 1994
25 Reconfigurable Computing: A Survey of Systems and Software - Compton, Hauck - 2002
23 RSIM: Simulating SharedMemory Multiprocessors with ILP Proce.. (context) - Hughes, Pai et al. - 2002
21 A simulation environment for hardware-software codesign (context) - Coumeri, Thomas - 1995
19 Morphosys: An Integrated Reconfigurable System for Data-Para.. (context) - Singh, Lee et al. - 2000
11 World Wide Web - Leon, Manual - 2003
9 REMARC: Reconfigurable Multimedia Array Coprocessor - Miyamori, Olukotun - 1998
8 Reconfigurable Computing Systems - Bondalapati, Prasanna - 2002
6 AMBA Specification (context) - Ltd - 1999
6 Software Timing Analysi Using HWSW Cosimulation and Instruct.. - Sangiovanni, Timing et al. - 1998
5 Synchronization Overhead Reduction in Timed Cosimulation - Yoo, Choi - 1997
4 MASE: A Novel Infrastructure for Detailed Microarchitectural.. (context) - Larson, Chatterjee et al. - 2001
3 engineering environment hardwaresoftware cosimulation - Tell, environment et al. - 1994
3 A formal approach to context scheduling for multicontext rec.. (context) - Maestre, Kurdahl et al. - 2001
3 A Reconfigurable System Featuring Dynamically Extensible Emb.. (context) - Borgatti, Lertora et al. - 2003
2 Survey HWSW Cosimulation Technique and Tool - of, Cosimulation et al. - 1998
2 Co-simulation of a Hybrid Multi-Context Architecture - Enzler, Plessl et al. - 2003
2 Mentor Graphics Corporation (context) - Hardware, Datasheet - 2003
1 ect of Reconfigurable Units in Superscalar Processors (context) - Carrillo, Chow - 2001
1 Augmenting a Processor with Reconfigurable Hardware (context) - Hauser - 2000
1 System-Level Modeling of Dynamically Reconfigurable Hardware.. (context) - Pelkonen, Masselos et al. - 2003
1 IEEE Design and Test of Computers (context) - Liem, Nacabal et al. - 1997
1 comproducttoolnexu pdk (context) - Co, Co et al. - 2003
1 XAPP151: Virtex Series Configuration Architecture User Guide (context) - Inc - 2003
1 cient VLSI Architecture for Lossless Data Compression (context) - Kim, Kim et al. - 1995
1 Hierarchical Simulation of a Multiprocessor Architecture - Pirvu, Bhuyan et al. - 2000
1 World Wide Web (context) - Logic, FPGA - 2003
Documents on the same site (http://knvikram.googlepages.com/publications.html):
Rate-distortion estimation for fast JPEG2000.. - Vikram, Vasudevan.. (2005) (Correct)
Mapping Data-Parallel Tasks Onto Partially Reconfigurable.. - Vikram, Vasudevan (2006) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC