Fast VLSI Binary Addition

Fast VLSI Binary Addition (1997)

Cached

Download Links

[www.ee.umn.edu]

by Keshab Parhi

Venue:	in Proc. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation
Citations:	1 - 0 self

Versions

Version History

Metadata Version 3

User correction supplied by SystemCorrections

Datum	Value	Source
TITLE	Fast VLSI Binary Addition	user correction - Legacy Corrections
AUTHOR NAME	Keshab Parhi	user correction - Legacy Corrections
AUTHOR AFFIL	Dept. of Electrical and Computer Engineering; University of Minnesota, Minneapolis	user correction - Legacy Corrections
AUTHOR ADDR	MN 55455, USA	user correction - Legacy Corrections
ABSTRACT	This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from W t fa to W tmux where t fa and tmux , respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carrygeneration component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W , is a power of two, then all carry signals can be generated in log2W tmux time using W (log2W \Gamma 1)+1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (W l...	user correction - Legacy Corrections
YEAR	1997	INFERENCE
VENUE	in Proc. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	232--241	INFERENCE
CITATIONS	13 found	ParsCit 1.0