Scan Testing of Asynchronous Sequential Circuits

Scan Testing of Asynchronous Sequential Circuits (1995)

by O. A. Petlin , S. B. Furber

Venue:	PROC. 5TH GREAT LAKES SYMPOSIUM ON VLSI
Citations:	6 - 3 self

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Datum	Value	Source
TITLE	Scan Testing of Asynchronous Sequential Circuits	user correction - Legacy Corrections
AUTHOR NAME	O. A. Petlin	user correction
AUTHOR AFFIL	Department of Computer Science, The University	user correction
AUTHOR ADDR	Oxford Road, Manchester, M13 9PL, U.K.	user correction
AUTHOR NAME	S. B. Furber	user correction
AUTHOR AFFIL	Department of Computer Science, The University	user correction
AUTHOR ADDR	Oxford Road, Manchester, M13 9PL, U.K.	user correction
ABSTRACT	A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques.	user correction
YEAR	1995	INFERENCE
VENUE	PROC. 5TH GREAT LAKES SYMPOSIUM ON VLSI	user correction
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	224--229	INFERENCE
CITATIONS	15 found	ParsCit 1.0