Time prediction in High Level Synthesis

Time prediction in High Level Synthesis

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by Marcos Luiz Mucheroni , Geraldo Lino de Campos , Renato da Silva Pereira , Campos Renato , Silva Pereira

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Datum	Value	Source
TITLE	Time prediction in High Level Synthesis	SVM HeaderParse 0.1
AUTHOR NAME	Marcos Luiz Mucheroni	user correction - Legacy Corrections
AUTHOR AFFIL	Summary	user correction - Legacy Corrections
AUTHOR NAME	Geraldo Lino de Campos	user correction - Legacy Corrections
AUTHOR AFFIL	Summary	user correction - Legacy Corrections
AUTHOR NAME	Renato da Silva Pereira	user correction - Legacy Corrections
AUTHOR NAME	Campos Renato	user correction - Legacy Corrections
AUTHOR AFFIL	Summary	user correction - Legacy Corrections
AUTHOR NAME	Silva Pereira	user correction - Legacy Corrections
AUTHOR AFFIL	Summary	user correction - Legacy Corrections
ABSTRACT	Introduction An important decision during implementation is at what level of abstraction and which tools will be used to build the system. Tools for software and hardware synthesis are needed at different levels, for example: flowcharts, algorithms, RTL descriptions, Boolean expressions, transistor and timing diagrams. Different tools have different power of expression, but also different levels of complexity during implementation in time and effort. The question that arises is what features are essential in a simple, fast and realistic system design. Thus, the HDL should be able to reduce drastically the effort required by the designer to express a particular feature of the design (e.g., resources, area and timing) without sacrificing the project itself. The implementation of timing and resources constraints are the most important facilities in many description styles and application domains. There is a difference between time constraints and time prediction; the former is n	user correction - Legacy Corrections
CITATIONS	14 found	ParsCit 1.0