BibTeX
@MISC{_microprocessorpower,
author = {},
title = {Microprocessor Power Analysis by Labeled Simulation 1},
year = {}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
In many applications, it is important to know how power is consumed while software is being executed on the target processor. Instruction-level power microanalysis, which is a cycle-accurate simulation technique based on instruction label generation and propagation, is aimed at answering this question for a superscalar and pipelined processor. This technique requires the micro-architectural details of the CPU and provides the power consumption of every module (or gate) for each active instruction in each cycle. To validate this approach, a Zilog digital signal processor corewasdesignedbyusinga0.25µ TSMC cell library, and the power consumption per instruction was collected using a Verilog simulator specially written for the DSP core. 1
Keyphrases
labeled simulation microprocessor power analysis power consumption instruction label generation micro-architectural detail cycle-accurate simulation technique active instruction verilog simulator many application dsp core zilog digital signal processor corewasdesignedbyusinga0 instruction-level power microanalysis tsmc cell library target processor
