Abstract

ABSTRACT — This paper presents a resource efficient reconfigurable hardware implementation of Advance Encryption Standard (AES) algorithm using High Level Language (HLL) approach on Field Programmable Gate Array (FPGA) for rapid development. In this work, we use an approach to directly map the design described in a high level package i.e. System Generator on FPGA platforms. This approach is ideal for Encryption functions where the development of data-path architectures can easily be done to provide bit and cycle accurate models. Our approach fills the gap between performance and flexibility by efficiently applying re-configurability. We use primitive level approach and customize all the operations our design by effectively utilizing conventional blocks of Xilinx System Generator to get optimum performance in terms of speed and area. This approach enables us to minimize critical paths in design and increase the overall frequency of design especially for MixColumn and SubByte transform. Our design shows best performance in terms of speed and area as compared with any other software and hardware/software co-design implementation counterparts, it operates at 288.19 MHZ and offers high throughput of 36.864 Gbps.