Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
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by
Victor Khomenko
,
Maciej Koutny
,
Alex Yakovlev
| Citations: | 22 - 6 self |
BibTeX
@MISC{Khomenko_logicsynthesis,
author = {Victor Khomenko and Maciej Koutny and Alex Yakovlev},
title = {Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT},
year = {}
}
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Abstract
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs.
