DMCA
PERFORMANCE ANALYSIS OF DOUBLE DIGIT DECIMAL MULTIPLIER ON VARIOUS FPGA LOGIC FAMILIES
BibTeX
@MISC{James_performanceanalysis,
author = {Rekha K. James and K. Poulose Jacob and Sreela Sasi},
title = {PERFORMANCE ANALYSIS OF DOUBLE DIGIT DECIMAL MULTIPLIER ON VARIOUS FPGA LOGIC FAMILIES},
year = {}
}
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Abstract
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of ª º1)2/ ( n cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard.
