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∗ This work was partially supported by grants from Conexant Systems Inc. and UC Micro (03-029) 1 Floorplan-aware Bus Architecture Synthesis ∗ (2004)
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@MISC{Pasricha04∗this,
author = {Sudeep Pasricha and Nikil Dutt and Elaheh Bozorgzadeh and Mohamed Ben-romdhane and Sudeep Pasricha and Nikil Dutt and Elaheh Bozorgzadeh and Mohamed Ben-romdhane},
title = {∗ This work was partially supported by grants from Conexant Systems Inc. and UC Micro (03-029) 1 Floorplan-aware Bus Architecture Synthesis ∗},
year = {2004}
}
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Abstract
As System-on-Chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this technical report, we address this problem by proposing an automated approach for synthesizing cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis flow also incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect timing violations early in the design flow. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected timing violations and generated core placements in a matter of hours instead of several days it took for a manual effort.
Keyphrases
floorplan-aware bus architecture synthesis uc micro conexant system inc communication architecture core placement several day synthesized bus architecture manual traversal bus architecture high-level floorplanning bus-based communication architecture performance constraint timing violation inter-component communication present case study performance requirement vast communication design space wire delay estimation engine automated approach technical report network communication soc subsystem detect timing violation design flow synthesis flow manual effort
