Toward kilo-instruction processors

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Toward kilo-instruction processors (2004)

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by Adrián Cristal , Oliverio J. Santana , Oliverio J. Santana , Mateo Valero , Mateo Valero

Venue:	ACM Transactions on Architecture and Code Optimization
Citations:	48 - 4 self

BibTeX

@ARTICLE{Cristal04towardkilo-instruction,
    author = {Adrián Cristal and Oliverio J. Santana and Oliverio J. Santana and Mateo Valero and Mateo Valero},
    title = {Toward kilo-instruction processors},
    journal = {ACM Transactions on Architecture and Code Optimization},
    year = {2004},
    volume = {1},
    pages = {10--25}
}

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Abstract

The continuously increasing gap between processor and memory speeds is a serious limitation to the performance achievable by future microprocessors. Currently, processors tolerate long-latency memory operations largely by maintaining a high number of in-flight instructions. In the future, this may require supporting many hundreds, or even thousands, of in-flight instructions. Unfortunately, the traditional approach of scaling up critical processor structures to provide such support is impractical at these levels, due to area, power, and cycle time constraints. In this paper we show that, in order to overcome this resource-scalability problem, the way in which critical processor resources are managed must be changed. Instead of simply upsizing the processor structures, we propose a smarter use of the available resources, supported by a selective checkpointing mechanism. This mechanism allows instructions to commit out of order, and makes a reorder buffer unnecessary. We present a set of techniques such as multilevel instruction queues, late allocation and early release of registers, and early release of load/store queue entries. All together, these techniques constitute what we call a kilo-instruction processor,anarchitecture that can support thousands of in-flight instructions, and thus may achieve high performance even in the presence of large memory access latencies.

Keyphrases

toward kilo-instruction processor in-flight instruction early release reorder buffer high number serious limitation selective checkpointing mechanism cycle time constraint critical processor structure high performance kilo-instruction processor long-latency memory operation late allocation many hundred future microprocessor available resource multilevel instruction queue processor structure critical processor resource resource-scalability problem load store queue entry memory speed large memory access latency smarter use traditional approach

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