DMCA
Hardware-managed register allocation for embedded processors (2004)
| Venue: | in LCTES ’04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and |
| Citations: | 4 - 1 self |
BibTeX
@INPROCEEDINGS{Zhuang04hardware-managedregister,
author = {Xiaotong Zhuang and Tao Zhang and Santosh Pande},
title = {Hardware-managed register allocation for embedded processors},
booktitle = {in LCTES ’04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and},
year = {2004},
pages = {192--201},
publisher = {ACM Press}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
Most modern processors (either embedded or general purpose) contain higher number of physical registers than those exposed in the ISA. Due to a variety of reasons, this phenomenon is likely to continue especially on embedded systems where encoding space is very limited. Saving the encoding space leads to lower power consumption in the I-cache; on the other hand, harnessing more physical registers saves power in the memory subsystem and reduces latency as well. These design decisions however result in the difficulty of register allocation for a compiler due to limited number of exposed registers at ISA level. In this paper, we therefore propose a hardware managed register allocation scheme to allocate more physical registers at runtime and to utilize them. As a byproduct, we also show that hardware managed register allocation has other merits such as better exploitation of low register pressure regions, more flexible management of caller-save/callee-save registers, etc. Our approach consists of both compiler and hardware enhancements. On the compiler side we assign variables at various stack offsets such that the offsets indicate the relative allocation priorities at runtime. The hardware is modified to identify such spills and make decisions whether they should be put in the (invisible) physical registers based on their relative priorities. Finally, our results show slight improvement in the instructions per cycle counts (IPC) but significant power consumption reduction in the cache.
Keyphrases
physical register embedded processor hardware-managed register allocation register allocation various stack offset register allocation scheme caller-save callee-save register relative priority hardware enhancement exposed register low register pressure region general purpose slight improvement modern processor significant power consumption reduction isa level memory subsystem reduces latency power consumption cycle count compiler side design decision relative allocation priority embedded system flexible management limited number
