The molen compiler for reconfigurable processors (2007)
| Venue: | ACM Transactions in Embedded Computing Systems (TECS |
| Citations: | 17 - 7 self |
BibTeX
@ARTICLE{Panainte07themolen,
author = {Elena Moscu Panainte and Koen Bertels and Stamatis Vassiliadis and Tu Delft},
title = {The molen compiler for reconfigurable processors},
journal = {ACM Transactions in Embedded Computing Systems (TECS},
year = {2007},
volume = {6}
}
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Abstract
In this paper, we describe the compiler developed to target the Molen reconfigurable processor and programming paradigm. The compiler automatically generates optimized binary code for C applications, based on pragma annotation of the code executed on the reconfigurable hardware. For the IBM PowerPC 405 processor included in the Virtex II Pro platform FPGA, we implemented code generation, register and stack frame allocation following the PowerPC EABI (Embedded Application Binary Interface). The PowerPC backend has been extended to generate the appropriate instructions for the reconfigurable hardware and data transfer, taking into account the information of the specific hardware implementations and system. Starting with an annotated C application, a complete design flow has been integrated to generate the executable bitstream for the reconfigurable processor. The flexible design of the proposed infrastructure allows to consider the special features of the reconfigurable architectures. In order to hide the reconfiguration latencies, we implemented an instruction scheduling algorithm for the dynamic hardware configuration instructions. The algorithm schedules in advance the hardware configuration instructions, taking into account the conflicts for the reconfigurable hardware resources (FPGA area) between the hardware operations. To verify the Molen compiler, we used the multimedia video frame
Keyphrases
molen compiler reconfigurable processor reconfigurable hardware hardware configuration instruction complete design flow reconfigurable hardware resource ibm powerpc flexible design reconfigurable architecture fpga area data transfer powerpc eabi specific hardware implementation code generation hardware operation embedded application binary interface stack frame allocation virtex ii pro platform fpga reconfiguration latency powerpc backend algorithm schedule multimedia video frame molen reconfigurable processor special feature executable bitstream programming paradigm appropriate instruction optimized binary code annotated application pragma annotation dynamic hardware configuration instruction
