SEED: Scalable, Efficient Enforcement of Dependences

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SEED: Scalable, Efficient Enforcement of Dependences

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by Francisco J. Mesa-martínez , Michael C. Huang , Jose Renau

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@MISC{Mesa-martínez_seed:scalable,,
    author = {Francisco J. Mesa-martínez and Michael C. Huang and Jose Renau},
    title = {SEED: Scalable, Efficient Enforcement of Dependences},
    year = {}
}

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Abstract

Instruction issue logic is a critical component in modern high-performance out-of-order processors. The ever increasing latencies found in modern processors, mostly associated with memory accesses and longer pipelines, can be attenuated using large issue queues. Conventional designs rely on atomic wakeup-select cycles to ensure compact scheduling. These designs must aggressively utilize broadcasting, compaction, and heavily-ported structures that scale poorly in terms of both power consumption and access time. To provide high scheduling flexibility and large instruction capacity without incurring prohibitive latency and energy overhead, we propose a novel scheme that uses an out-oforder, broadcast-free instruction wakeup block feeding an in-order scheduler. Multi-banked, index-based structures are used throughout this scheme to provide a high degree of scalability while achieving efficient dependence tracking, resulting in good overall performance and energy efficiency. We call this design “Scalable, Efficient Enforcement of Dependences (SEED)”. We present a detailed design and analysis of SEED through an extensive evaluation. Compared to a conventional issue queue design, which is assumed favorably to scale in size without any impact on cycle time, the performance degradation of our design is 3 % for both INT and FP suites of SPEC CPU2000. For such a small performance cost, SEED enjoys a 19 % reduction in total chip power consumption for a 32-entry configuration. We also synthesize SEED and a conventional issue logic with 90nm standard cell logic. Synthesis results show that SEED can cycle twice the speed of a conventional issue logic of equivalent size. Cycling at the same frequency, SEED consumes ten times less dynamic power and five times less static power while achieving substantial area savings.

Keyphrases

efficient enforcement conventional issue logic compact scheduling total chip power consumption substantial area saving detailed design large instruction capacity modern high-performance out-of-order processor heavily-ported structure spec cpu2000 fp suite atomic wakeup-select cycle small performance cost good overall performance high degree power consumption ten time modern processor extensive evaluation memory access dynamic power conventional design prohibitive latency in-order scheduler design scalable novel scheme energy overhead instruction issue logic performance degradation conventional issue queue design standard cell logic energy efficiency broadcast-free instruction wakeup block critical component access time index-based structure efficient dependence tracking 32-entry configuration large issue queue static power cycle time equivalent size synthesis result

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