BibTeX
@MISC{_microprocessorpower,
author = {},
title = {Microprocessor Power Analysis by Labeled Simulation},
year = {}
}
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Abstract
Abstract ⎯ In many applications, it is important to know how power is consumed while software is being executed on the target processor. Instruction level power microanalysis, which is a cycleaccurate simulation technique based on instruction label generation and propagation, is aimed at answering this question for a superscalar and pipelined processor. This technique requires the micro-architectural details of the CPU and provides the power consumption of every module (or gate) for each active instruction in each cycle. To validate the approach, a Zilog DSP core was designed by using a 0.25µ TSMC cell library and the power consumption per instruction was collected using a Verilog simulator specially written for the DSP core. I.
Keyphrases
labeled simulation microprocessor power analysis power consumption active instruction verilog simulator micro-architectural detail many application dsp core instruction level power microanalysis zilog dsp core tsmc cell library target processor instruction label generation cycleaccurate simulation technique
